   This file documents the GNU Assembler "as".

   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002
Free Software Foundation, Inc.

   Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.1 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts.  A copy of the license is included in the section entitled "GNU
Free Documentation License".

80386 Dependent Features
========================

   The i386 version `as' supports both the original Intel 386
architecture in both 16 and 32-bit mode as well as AMD x86-64
architecture extending the Intel architecture to 64-bits.

Options
-------

   The i386 version of `as' has a few machine dependent options:

`--32 | --64'
     Select the word size, either 32 bits or 64 bits. Selecting 32-bit
     implies Intel i386 architecture, while 64-bit implies AMD x86-64
     architecture.

     These options are only available with the ELF object file format,
     and require that the necessary BFD support has been included (on a
     32-bit platform you have to add -enable-64-bit-bfd to configure
     enable 64-bit usage and use x86-64 as target platform).

AT&T Syntax versus Intel Syntax
-------------------------------

   `as' now supports assembly using Intel assembler syntax.
`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
the usual AT&T mode for compatibility with the output of `gcc'.  Either
of these directives may have an optional argument, `prefix', or
`noprefix' specifying whether registers require a `%' prefix.  AT&T
System V/386 assembler syntax is quite different from Intel syntax.  We
mention these differences because almost all 80386 documents use Intel
syntax.  Notable differences between the two syntaxes are:

   * AT&T immediate operands are preceded by `$'; Intel immediate
     operands are undelimited (Intel `push 4' is AT&T `pushl $4').
     AT&T register operands are preceded by `%'; Intel register operands
     are undelimited.  AT&T absolute (as opposed to PC relative)
     jump/call operands are prefixed by `*'; they are undelimited in
     Intel syntax.

   * AT&T and Intel syntax use the opposite order for source and
     destination operands.  Intel `add eax, 4' is `addl $4, %eax'.  The
     `source, dest' convention is maintained for compatibility with
     previous Unix assemblers.  Note that instructions with more than
     one source operand, such as the `enter' instruction, do _not_ have
     reversed order.  See i386-Bugs.

   * In AT&T syntax the size of memory operands is determined from the
     last character of the instruction mnemonic.  Mnemonic suffixes of
     `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
     (32-bit) and quadruple word (64-bit) memory references.  Intel
     syntax accomplishes this by prefixing memory operands (_not_ the
     instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
     and `qword ptr'.  Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
     %al' in AT&T syntax.

   * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
     $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
     SECTION:OFFSET'.  Also, the far return instruction is `lret
     $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
     STACK-ADJUST'.

   * The AT&T assembler does not provide support for multiple section
     programs.  Unix style systems expect all programs to be single
     sections.

Instruction Naming
------------------

   Instruction mnemonics are suffixed with one character modifiers which
specify the size of operands.  The letters `b', `w', `l' and `q'
specify byte, word, long and quadruple word operands.  If no suffix is
specified by an instruction then `as' tries to fill in the missing
suffix based on the destination register operand (the last one by
convention).  Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
also, `mov $1, %bx' is equivalent to `movw $1, bx'.  Note that this is
incompatible with the AT&T Unix assembler which assumes that a missing
mnemonic suffix implies long operand size.  (This incompatibility does
not affect compiler output since compilers always explicitly specify
the mnemonic suffix.)

   Almost all instructions have the same names in AT&T and Intel format.
There are a few exceptions.  The sign extend and zero extend
instructions need two sizes to specify them.  They need a size to
sign/zero extend _from_ and a size to zero extend _to_.  This is
accomplished by using two instruction mnemonic suffixes in AT&T syntax.
Base names for sign extend and zero extend are `movs...' and `movz...'
in AT&T syntax (`movsx' and `movzx' in Intel syntax).  The instruction
mnemonic suffixes are tacked on to this base name, the _from_ suffix
before the _to_ suffix.  Thus, `movsbl %al, %edx' is AT&T syntax for
"move sign extend _from_ %al _to_ %edx."  Possible suffixes, thus, are
`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
word), and `lq' (from long to quadruple word).

   The Intel-syntax conversion instructions

   * `cbw' -- sign-extend byte in `%al' to word in `%ax',

   * `cwde' -- sign-extend word in `%ax' to long in `%eax',

   * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',

   * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',

   * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
     only),

   * `cdo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
     (x86-64 only),

are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
naming.  `as' accepts either naming for these instructions.

   Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
but are `call far' and `jump far' in Intel convention.

Register Naming
---------------

   Register operands are always prefixed with `%'.  The 80386 registers
consist of

   * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
     `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
     (the stack pointer).

   * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
     `%si', `%bp', and `%sp'.

   * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
     `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
     `%bx', `%cx', and `%dx')

   * the 6 section registers `%cs' (code section), `%ds' (data
     section), `%ss' (stack section), `%es', `%fs', and `%gs'.

   * the 3 processor control registers `%cr0', `%cr2', and `%cr3'.

   * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
     `%db7'.

   * the 2 test registers `%tr6' and `%tr7'.

   * the 8 floating point register stack `%st' or equivalently
     `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
     `%st(6)', and `%st(7)'.  These registers are overloaded by 8 MMX
     registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
     and `%mm7'.

   * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3',
     `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.

   The AMD x86-64 architecture extends the register set by:

   * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
     accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
     frame pointer), `%rsp' (the stack pointer)

   * the 8 extended registers `%r8'-`%r15'.

   * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'

   * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'

   * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'

   * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.

   * the 8 debug registers: `%db8'-`%db15'.

   * the 8 SSE registers: `%xmm8'-`%xmm15'.

Instruction Prefixes
--------------------

   Instruction prefixes are used to modify the following instruction.
They are used to repeat string instructions, to provide section
overrides, to perform bus lock operations, and to change operand and
address sizes.  (Most instructions that normally operate on 32-bit
operands will use 16-bit operands if the instruction has an "operand
size" prefix.)  Instruction prefixes are best written on the same line
as the instruction they act upon. For example, the `scas' (scan string)
instruction is repeated with:

             repne scas %es:(%edi),%al

   You may also place prefixes on the lines immediately preceding the
instruction, but this circumvents checks that `as' does with prefixes,
and will not work with all prefixes.

   Here is a list of instruction prefixes:

   * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
     These are automatically added by specifying using the
     SECTION:MEMORY-OPERAND form for memory references.

   * Operand/Address size prefixes `data16' and `addr16' change 32-bit
     operands/addresses into 16-bit operands/addresses, while `data32'
     and `addr32' change 16-bit ones (in a `.code16' section) into
     32-bit operands/addresses.  These prefixes _must_ appear on the
     same line of code as the instruction they modify. For example, in
     a 16-bit `.code16' section, you might write:

                  addr32 jmpl *(%ebx)

   * The bus lock prefix `lock' inhibits interrupts during execution of
     the instruction it precedes.  (This is only valid with certain
     instructions; see a 80386 manual for details).

   * The wait for coprocessor prefix `wait' waits for the coprocessor to
     complete the current instruction.  This should never be needed for
     the 80386/80387 combination.

   * The `rep', `repe', and `repne' prefixes are added to string
     instructions to make them repeat `%ecx' times (`%cx' times if the
     current address size is 16-bits).

   * The `rex' family of prefixes is used by x86-64 to encode
     extensions to i386 instruction set.  The `rex' prefix has four
     bits -- an operand size overwrite (`64') used to change operand
     size from 32-bit to 64-bit and X, Y and Z extensions bits used to
     extend the register set.

     You may write the `rex' prefixes directly. The `rex64xyz'
     instruction emits `rex' prefix with all the bits set.  By omitting
     the `64', `x', `y' or `z' you may write other prefixes as well.
     Normally, there is no need to write the prefixes explicitly, since
     gas will automatically generate them based on the instruction
     operands.

Memory References
-----------------

   An Intel syntax indirect memory reference of the form

     SECTION:[BASE + INDEX*SCALE + DISP]

is translated into the AT&T syntax

     SECTION:DISP(BASE, INDEX, SCALE)

where BASE and INDEX are the optional 32-bit base and index registers,
DISP is the optional displacement, and SCALE, taking the values 1, 2,
4, and 8, multiplies INDEX to calculate the address of the operand.  If
no SCALE is specified, SCALE is taken to be 1.  SECTION specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&T syntax _must_ be
preceded by a `%'.  If you specify a section override which coincides
with the default section register, `as' does _not_ output any section
register override prefixes to assemble the given instruction.  Thus,
section overrides can be specified to emphasize which section register
is used for a given memory operand.

   Here are some examples of Intel and AT&T style memory references:

AT&T: `-4(%ebp)', Intel:  `[ebp - 4]'
     BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
     section is used (`%ss' for addressing with `%ebp' as the base
     register).  INDEX, SCALE are both missing.

AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
     INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'.  All other
     fields are missing.  The section register here defaults to `%ds'.

AT&T: `foo(,1)'; Intel `[foo]'
     This uses the value pointed to by `foo' as a memory operand.  Note
     that BASE and INDEX are both missing, but there is only _one_ `,'.
     This is a syntactic exception.

AT&T: `%gs:foo'; Intel `gs:foo'
     This selects the contents of the variable `foo' with section
     register SECTION being `%gs'.

   Absolute (as opposed to PC relative) call and jump operands must be
prefixed with `*'.  If no `*' is specified, `as' always chooses PC
relative addressing for jump/call labels.

   Any instruction that has a memory operand, but no register operand,
_must_ specify its size (byte, word, long, or quadruple) with an
instruction mnemonic suffix (`b', `w', `l' or `q', respectively).

   The x86-64 architecture adds an RIP (instruction pointer relative)
addressing.  This addressing mode is specified by using `rip' as a base
register.  Only constant offsets are valid. For example:

AT&T: `1234(%rip)', Intel: `[rip + 1234]'
     Points to the address 1234 bytes past the end of the current
     instruction.

AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
     Points to the `symbol' in RIP relative way, this is shorter than
     the default absolute addressing.

   Other addressing modes remain unchanged in x86-64 architecture,
except registers used are 64-bit instead of 32-bit.

Handling of Jump Instructions
-----------------------------

   Jump instructions are always optimized to use the smallest possible
displacements.  This is accomplished by using byte (8-bit) displacement
jumps whenever the target is sufficiently close.  If a byte displacement
is insufficient a long displacement is used.  We do not support word
(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
instruction with the `data16' instruction prefix), since the 80386
insists upon masking `%eip' to 16 bits after the word displacement is
added. (See also i386-Arch)

   Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
and `loopne' instructions only come in byte displacements, so that if
you use these instructions (`gcc' does not use them) you may get an
error message (and incorrect code).  The AT&T 80386 assembler tries to
get around this problem by expanding `jcxz foo' to

              jcxz cx_zero
              jmp cx_nonzero
     cx_zero: jmp foo
     cx_nonzero:

Floating Point
--------------

   All 80387 floating point types except packed BCD are supported.
(BCD support may be added without much difficulty).  These data types
are 16-, 32-, and 64- bit integers, and single (32-bit), double
(64-bit), and extended (80-bit) precision floating point.  Each
supported type has an instruction mnemonic suffix and a constructor
associated with it.  Instruction mnemonic suffixes specify the operand's
data type.  Constructors build these data types into memory.

   * Floating point constructors are `.float' or `.single', `.double',
     and `.tfloat' for 32-, 64-, and 80-bit formats.  These correspond
     to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
     80-bit (ten byte) real.  The 80387 only supports this format via
     the `fldt' (load 80-bit real to stack top) and `fstpt' (store
     80-bit real and pop stack) instructions.

   * Integer constructors are `.word', `.long' or `.int', and `.quad'
     for the 16-, 32-, and 64-bit integer formats.  The corresponding
     instruction mnemonic suffixes are `s' (single), `l' (long), and
     `q' (quad).  As with the 80-bit real format, the 64-bit `q' format
     is only present in the `fildq' (load quad integer to stack top)
     and `fistpq' (store quad integer and pop stack) instructions.

   Register to register operations should not use instruction mnemonic
suffixes.  `fstl %st, %st(1)' will give a warning, and be assembled as
if you wrote `fst %st, %st(1)', since all register to register
operations use 80-bit floating point operands. (Contrast this with
`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
point format, then stores the result in the 4 byte location `mem')

Intel's MMX and AMD's 3DNow! SIMD Operations
--------------------------------------------

   `as' supports Intel's MMX instruction set (SIMD instructions for
integer data), available on Intel's Pentium MMX processors and Pentium
II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
probably others.  It also supports AMD's 3DNow!  instruction set (SIMD
instructions for 32-bit floating point data) available on AMD's K6-2
processor and possibly others in the future.

   Currently, `as' does not support Intel's floating point SIMD, Katmai
(KNI).

   The eight 64-bit MMX operands, also used by 3DNow!, are called
`%mm0', `%mm1', ... `%mm7'.  They contain eight 8-bit integers, four
16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
floating point values.  The MMX registers cannot be used at the same
time as the floating point stack.

   See Intel and AMD documentation, keeping in mind that the operand
order in instructions is reversed from the Intel syntax.

Writing 16-bit Code
-------------------

   While `as' normally writes only "pure" 32-bit i386 code or 64-bit
x86-64 code depending on the default configuration, it also supports
writing code to run in real mode or in 16-bit protected mode code
segments.  To do this, put a `.code16' or `.code16gcc' directive before
the assembly language instructions to be run in 16-bit mode.  You can
switch `as' back to writing normal 32-bit code with the `.code32'
directive.

   `.code16gcc' provides experimental support for generating 16-bit
code from gcc, and differs from `.code16' in that `call', `ret',
`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
instructions default to 32-bit size.  This is so that the stack pointer
is manipulated in the same way over function calls, allowing access to
function parameters at the same stack offsets as in 32-bit mode.
`.code16gcc' also automatically adds address size prefixes where
necessary to use the 32-bit addressing modes that gcc generates.

   The code which `as' generates in 16-bit mode will not necessarily
run on a 16-bit pre-80386 processor.  To write code that runs on such a
processor, you must refrain from using _any_ 32-bit constructs which
require `as' to output address or operand size prefixes.

   Note that writing 16-bit code instructions by explicitly specifying a
prefix or an instruction mnemonic suffix within a 32-bit code section
generates different machine instructions than those generated for a
16-bit code segment.  In a 32-bit code section, the following code
generates the machine opcode bytes `66 6a 04', which pushes the value
`4' onto the stack, decrementing `%esp' by 2.

             pushw $4

   The same code in a 16-bit code section would generate the machine
opcode bytes `6a 04' (ie. without the operand size prefix), which is
correct since the processor default operand size is assumed to be 16
bits in a 16-bit code section.

AT&T Syntax bugs
----------------

   The UnixWare assembler, and probably other AT&T derived ix86 Unix
assemblers, generate floating point instructions with reversed source
and destination registers in certain cases.  Unfortunately, gcc and
possibly many other programs use this reversed syntax, so we're stuck
with it.

   For example

             fsub %st,%st(3)

results in `%st(3)' being updated to `%st - %st(3)' rather than the
expected `%st(3) - %st'.  This happens with all the non-commutative
arithmetic floating point operations with two register operands where
the source register is `%st' and the destination register is `%st(i)'.

Specifying CPU Architecture
---------------------------

   `as' may be told to assemble for a particular CPU architecture with
the `.arch CPU_TYPE' directive.  This directive enables a warning when
gas detects an instruction that is not supported on the CPU specified.
The choices for CPU_TYPE are:

`i8086'        `i186'         `i286'         `i386'
`i486'         `i586'         `i686'         `pentium'
`pentiumpro'   `pentium4'     `k6'           `athlon'
`sledgehammer'

   Apart from the warning, there are only two other effects on `as'
operation;  Firstly, if you specify a CPU other than `i486', then shift
by one instructions such as `sarl $1, %eax' will automatically use a
two byte opcode sequence.  The larger three byte opcode sequence is
used on the 486 (and when no architecture is specified) because it
executes faster on the 486.  Note that you can explicitly request the
two byte opcode by writing `sarl %eax'.  Secondly, if you specify
`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
offset conditional jumps will be promoted when necessary to a two
instruction sequence consisting of a conditional jump of the opposite
sense around an unconditional jump to the target.

   Following the CPU architecture, you may specify `jumps' or `nojumps'
to control automatic promotion of conditional jumps.  `jumps' is the
default, and enables jump promotion;  All external jumps will be of the
long variety, and file-local jumps will be promoted as necessary.
(see i386-Jumps)  `nojumps' leaves external conditional jumps as
byte offset jumps, and warns about file-local conditional jumps that
`as' promotes.  Unconditional jumps are treated as for `jumps'.

   For example

      .arch i8086,nojumps

Notes
-----

   There is some trickery concerning the `mul' and `imul' instructions
that deserves mention.  The 16-, 32-, 64- and 128-bit expanding
multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
can be output only in the one operand form.  Thus, `imul %ebx, %eax'
does _not_ select the expanding multiply; the expanding multiply would
clobber the `%edx' register, and this would confuse `gcc' output.  Use
`imul %ebx' to get the 64-bit product in `%edx:%eax'.

   We have added a two operand form of `imul' when the first operand is
an immediate mode expression and the second operand is a register.
This is just a shorthand, so that, multiplying `%eax' by 69, for
example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
%eax'.

Intel i860 Dependent Features
=============================

i860 Notes
----------

   This is a fairly complete i860 assembler which is compatible with the
UNIX System V/860 Release 4 assembler. However, it does not currently
support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').

   Like the SVR4/860 assembler, the output object format is ELF32.
Currently, this is the only supported object format. If there is
sufficient interest, other formats such as COFF may be implemented.

i860 Command-line Options
-------------------------

SVR4 compatibility options
..........................

`-V'
     Print assembler version.

`-Qy'
     Ignored.

`-Qn'
     Ignored.

Other options
.............

`-EL'
     Select little endian output (this is the default).

`-EB'
     Select big endian output. Note that the i860 always reads
     instructions as little endian data, so this option only effects
     data and not instructions.

`-mwarn-expand'
     Emit a warning message if any pseudo-instruction expansions
     occurred.  For example, a `or' instruction with an immediate
     larger than 16-bits will be expanded into two instructions. This
     is a very undesirable feature to rely on, so this flag can help
     detect any code where it happens. One use of it, for instance, has
     been to find and eliminate any place where `gcc' may emit these
     pseudo-instructions.

i860 Machine Directives
-----------------------

`.dual'
     Enter dual instruction mode. While this directive is supported, the
     preferred way to use dual instruction mode is to explicitly code
     the dual bit with the `d.' prefix.

`.enddual'
     Exit dual instruction mode. While this directive is supported, the
     preferred way to use dual instruction mode is to explicitly code
     the dual bit with the `d.' prefix.

`.atmp'
     Change the temporary register used when expanding pseudo
     operations. The default register is `r31'.

i860 Opcodes
------------

   All of the Intel i860 machine instructions are supported. Please see
either _i860 Microprocessor Programmer's Reference Manual_ or _i860
Microprocessor Architecture_ for more information.

Other instruction support (pseudo-instructions)
...............................................

   For compatibility with some other i860 assemblers, a number of
pseudo-instructions are supported. While these are supported, they are
a very undesirable feature that should be avoided - in particular, when
they result in an expansion to multiple actual i860 instructions. Below
are the pseudo-instructions that result in expansions.
   * Load large immediate into general register:

     The pseudo-instruction `mov imm,%rn' (where the immediate does not
     fit within a signed 16-bit field) will be expanded into:
          orh large_imm@h,%r0,%rn
          or large_imm@l,%rn,%rn

   * Load/store with relocatable address expression:

     For example, the pseudo-instruction `ld.b addr,%rn' will be
     expanded into:
          orh addr_exp@ha,%r0,%r31
          ld.l addr_exp@l(%r31),%rn

     The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
     fst.x', and `pst.x' as well.

   * Signed large immediate with add/subtract:

     If any of the arithmetic operations `adds, addu, subs, subu' are
     used with an immediate larger than 16-bits (signed), then they
     will be expanded.  For instance, the pseudo-instruction `adds
     large_imm,%rx,%rn' expands to:
          orh large_imm@h,%r0,%r31
          or large_imm@l,%r31,%r31
          adds %r31,%rx,%rn

   * Unsigned large immediate with logical operations:

     Logical operations (`or, andnot, or, xor') also result in
     expansions.  The pseudo-instruction `or large_imm,%rx,%rn' results
     in:
          orh large_imm@h,%rx,%r31
          or large_imm@l,%r31,%rn

     Similarly for the others, except for `and' which expands to:
          andnot (-1 - large_imm)@h,%rx,%r31
          andnot (-1 - large_imm)@l,%r31,%rn

Intel 80960 Dependent Features
==============================

i960 Command-line Options
-------------------------

`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
     Select the 80960 architecture.  Instructions or features not
     supported by the selected architecture cause fatal errors.

     `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
     Synonyms are provided for compatibility with other tools.

     If you do not specify any of these options, `as' generates code
     for any instruction or feature that is supported by _some_ version
     of the 960 (even if this means mixing architectures!).  In
     principle, `as' attempts to deduce the minimal sufficient
     processor type if none is specified; depending on the object code
     format, the processor type may be recorded in the object file.  If
     it is critical that the `as' output match a specific architecture,
     specify that architecture explicitly.

`-b'
     Add code to collect information about conditional branches taken,
     for later optimization using branch prediction bits.  (The
     conditional branch instructions have branch prediction bits in the
     CA, CB, and CC architectures.)  If BR represents a conditional
     branch instruction, the following represents the code generated by
     the assembler when `-b' is specified:

                  call    INCREMENT ROUTINE
                  .word   0       # pre-counter
          Label:  BR
                  call    INCREMENT ROUTINE
                  .word   0       # post-counter

     The counter following a branch records the number of times that
     branch was _not_ taken; the differenc between the two counters is
     the number of times the branch _was_ taken.

     A table of every such `Label' is also generated, so that the
     external postprocessor `gbr960' (supplied by Intel) can locate all
     the counters.  This table is always labelled `__BRANCH_TABLE__';
     this is a local symbol to permit collecting statistics for many
     separate object files.  The table is word aligned, and begins with
     a two-word header.  The first word, initialized to 0, is used in
     maintaining linked lists of branch tables.  The second word is a
     count of the number of entries in the table, which follow
     immediately: each is a word, pointing to one of the labels
     illustrated above.

           +------------+------------+------------+ ... +------------+
           |            |            |            |     |            |
           |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
           |            |            |            |     |            |
           +------------+------------+------------+ ... +------------+

                         __BRANCH_TABLE__ layout

     The first word of the header is used to locate multiple branch
     tables, since each object file may contain one. Normally the links
     are maintained with a call to an initialization routine, placed at
     the beginning of each function in the file.  The GNU C compiler
     generates these calls automatically when you give it a `-b' option.
     For further details, see the documentation of `gbr960'.

`-no-relax'
     Normally, Compare-and-Branch instructions with targets that require
     displacements greater than 13 bits (or that have external targets)
     are replaced with the corresponding compare (or `chkbit') and
     branch instructions.  You can use the `-no-relax' option to
     specify that `as' should generate errors instead, if the target
     displacement is larger than 13 bits.

     This option does not affect the Compare-and-Jump instructions; the
     code emitted for them is _always_ adjusted when necessary
     (depending on displacement size), regardless of whether you use
     `-no-relax'.

Floating Point
--------------

   `as' generates IEEE floating-point numbers for the directives
`.float', `.double', `.extended', and `.single'.

i960 Machine Directives
-----------------------

`.bss SYMBOL, LENGTH, ALIGN'
     Reserve LENGTH bytes in the bss section for a local SYMBOL,
     aligned to the power of two specified by ALIGN.  LENGTH and ALIGN
     must be positive absolute expressions.  This directive differs
     from `.lcomm' only in that it permits you to specify an alignment.
     See `.lcomm'.

`.extended FLONUMS'
     `.extended' expects zero or more flonums, separated by commas; for
     each flonum, `.extended' emits an IEEE extended-format (80-bit)
     floating-point number.

`.leafproc CALL-LAB, BAL-LAB'
     You can use the `.leafproc' directive in conjunction with the
     optimized `callj' instruction to enable faster calls of leaf
     procedures.  If a procedure is known to call no other procedures,
     you may define an entry point that skips procedure prolog code
     (and that does not depend on system-supplied saved context), and
     declare it as the BAL-LAB using `.leafproc'.  If the procedure
     also has an entry point that goes through the normal prolog, you
     can specify that entry point as CALL-LAB.

     A `.leafproc' declaration is meant for use in conjunction with the
     optimized call instruction `callj'; the directive records the data
     needed later to choose between converting the `callj' into a `bal'
     or a `call'.

     CALL-LAB is optional; if only one argument is present, or if the
     two arguments are identical, the single argument is assumed to be
     the `bal' entry point.

`.sysproc NAME, INDEX'
     The `.sysproc' directive defines a name for a system procedure.
     After you define it using `.sysproc', you can use NAME to refer to
     the system procedure identified by INDEX when calling procedures
     with the optimized call instruction `callj'.

     Both arguments are required; INDEX must be between 0 and 31
     (inclusive).

i960 Opcodes
------------

   All Intel 960 machine instructions are supported; see i960 Command-line Options
for a discussion of selecting the
instruction subset for a particular 960 architecture.

   Some opcodes are processed beyond simply emitting a single
corresponding instruction: `callj', and Compare-and-Branch or
Compare-and-Jump instructions with target displacements larger than 13
bits.

`callj'
.......

   You can write `callj' to have the assembler or the linker determine
the most appropriate form of subroutine call: `call', `bal', or
`calls'.  If the assembly source contains enough information--a
`.leafproc' or `.sysproc' directive defining the operand--then `as'
translates the `callj'; if not, it simply emits the `callj', leaving it
for the linker to resolve.

Compare-and-Branch
..................

   The 960 architectures provide combined Compare-and-Branch
instructions that permit you to store the branch target in the lower 13
bits of the instruction word itself.  However, if you specify a branch
target far enough away that its address won't fit in 13 bits, the
assembler can either issue an error, or convert your Compare-and-Branch
instruction into separate instructions to do the compare and the branch.

   Whether `as' gives an error or expands the instruction depends on
two choices you can make: whether you use the `-no-relax' option, and
whether you use a "Compare and Branch" instruction or a "Compare and
Jump" instruction.  The "Jump" instructions are _always_ expanded if
necessary; the "Branch" instructions are expanded when necessary
_unless_ you specify `-no-relax'--in which case `as' gives an error
instead.

   These are the Compare-and-Branch instructions, their "Jump" variants,
and the instruction pairs they may expand into:

             Compare and
          Branch      Jump       Expanded to
          ------    ------       ------------
             bbc                 chkbit; bno
             bbs                 chkbit; bo
          cmpibe    cmpije       cmpi; be
          cmpibg    cmpijg       cmpi; bg
         cmpibge   cmpijge       cmpi; bge
          cmpibl    cmpijl       cmpi; bl
         cmpible   cmpijle       cmpi; ble
         cmpibno   cmpijno       cmpi; bno
         cmpibne   cmpijne       cmpi; bne
          cmpibo    cmpijo       cmpi; bo
          cmpobe    cmpoje       cmpo; be
          cmpobg    cmpojg       cmpo; bg
         cmpobge   cmpojge       cmpo; bge
          cmpobl    cmpojl       cmpo; bl
         cmpoble   cmpojle       cmpo; ble
         cmpobne   cmpojne       cmpo; bne

M32R Dependent Features
=======================

M32R Options
------------

   The Mitsubishi M32R version of `as' has a few machine dependent
options:

`-m32rx'
     `as' can assemble code for several different members of the
     Mitsubishi M32R family.  Normally the default is to assemble code
     for the M32R microprocessor.  This option may be used to change
     the default to the M32RX microprocessor, which adds some more
     instructions to the basic M32R instruction set, and some
     additional parameters to some of the original instructions.

`-m32r'
     This option can be used to restore the assembler's default
     behaviour of assembling for the M32R microprocessor.  This can be
     useful if the default has been changed by a previous command line
     option.

`-warn-explicit-parallel-conflicts'
     Instructs `as' to produce warning messages when questionable
     parallel instructions are encountered.  This option is enabled by
     default, but `gcc' disables it when it invokes `as' directly.
     Questionable instructions are those whoes behaviour would be
     different if they were executed sequentially.  For example the
     code fragment `mv r1, r2 || mv r3, r1' produces a different result
     from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
     and then r2 into r1, whereas the later moves r2 into r1 and r3.

`-Wp'
     This is a shorter synonym for the
     _-warn-explicit-parallel-conflicts_ option.

`-no-warn-explicit-parallel-conflicts'
     Instructs `as' not to produce warning messages when questionable
     parallel instructions are encountered.

`-Wnp'
     This is a shorter synonym for the
     _-no-warn-explicit-parallel-conflicts_ option.

M32R Warnings
-------------

   There are several warning and error messages that can be produced by
`as' which are specific to the M32R:

`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
     This message is only produced if warnings for explicit parallel
     conflicts have been enabled.  It indicates that the assembler has
     encountered a parallel instruction in which the destination
     register of the left hand instruction is used as an input register
     in the right hand instruction.  For example in this code fragment
     `mv r1, r2 || neg r3, r1' register r1 is the destination of the
     move instruction and the input to the neg instruction.

`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
     This message is only produced if warnings for explicit parallel
     conflicts have been enabled.  It indicates that the assembler has
     encountered a parallel instruction in which the destination
     register of the right hand instruction is used as an input
     register in the left hand instruction.  For example in this code
     fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
     of the neg instruction and the input to the move instruction.

`instruction `...' is for the M32RX only'
     This message is produced when the assembler encounters an
     instruction which is only supported by the M32Rx processor, and
     the `-m32rx' command line flag has not been specified to allow
     assembly of such instructions.

`unknown instruction `...''
     This message is produced when the assembler encounters an
     instruction which it doe snot recognise.

`only the NOP instruction can be issued in parallel on the m32r'
     This message is produced when the assembler encounters a parallel
     instruction which does not involve a NOP instruction and the
     `-m32rx' command line flag has not been specified.  Only the M32Rx
     processor is able to execute two instructions in parallel.

`instruction `...' cannot be executed in parallel.'
     This message is produced when the assembler encounters a parallel
     instruction which is made up of one or two instructions which
     cannot be executed in parallel.

`Instructions share the same execution pipeline'
     This message is produced when the assembler encounters a parallel
     instruction whoes components both use the same execution pipeline.

`Instructions write to the same destination register.'
     This message is produced when the assembler encounters a parallel
     instruction where both components attempt to modify the same
     register.  For example these code fragments will produce this
     message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
     @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
     r3, r4' (Both write to the condition bit)

M680x0 Dependent Features
=========================

M680x0 Options
--------------

   The Motorola 680x0 version of `as' has a few machine dependent
options:

`-l'
     You can use the `-l' option to shorten the size of references to
     undefined symbols.  If you do not use the `-l' option, references
     to undefined symbols are wide enough for a full `long' (32 bits).
     (Since `as' cannot know where these symbols end up, `as' can only
     allocate space for the linker to fill in later.  Since `as' does
     not know how far away these symbols are, it allocates as much
     space as it can.)  If you use this option, the references are only
     one word wide (16 bits).  This may be useful if you want the
     object file to be as small as possible, and you know that the
     relevant symbols are always less than 17 bits away.

`--register-prefix-optional'
     For some configurations, especially those where the compiler
     normally does not prepend an underscore to the names of user
     variables, the assembler requires a `%' before any use of a
     register name.  This is intended to let the assembler distinguish
     between C variables and functions named `a0' through `a7', and so
     on.  The `%' is always accepted, but is not required for certain
     configurations, notably `sun3'.  The `--register-prefix-optional'
     option may be used to permit omitting the `%' even for
     configurations for which it is normally required.  If this is
     done, it will generally be impossible to refer to C variables and
     functions with the same names as register names.

`--bitwise-or'
     Normally the character `|' is treated as a comment character, which
     means that it can not be used in expressions.  The `--bitwise-or'
     option turns `|' into a normal character.  In this mode, you must
     either use C style comments, or start comments with a `#' character
     at the beginning of a line.

`--base-size-default-16  --base-size-default-32'
     If you use an addressing mode with a base register without
     specifying the size, `as' will normally use the full 32 bit value.
     For example, the addressing mode `%a0@(%d0)' is equivalent to
     `%a0@(%d0:l)'.  You may use the `--base-size-default-16' option to
     tell `as' to default to using the 16 bit value.  In this case,
     `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'.  You may use the
     `--base-size-default-32' option to restore the default behaviour.

`--disp-size-default-16  --disp-size-default-32'
     If you use an addressing mode with a displacement, and the value
     of the displacement is not known, `as' will normally assume that
     the value is 32 bits.  For example, if the symbol `disp' has not
     been defined, `as' will assemble the addressing mode
     `%a0@(disp,%d0)' as though `disp' is a 32 bit value.  You may use
     the `--disp-size-default-16' option to tell `as' to instead assume
     that the displacement is 16 bits.  In this case, `as' will
     assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value.  You
     may use the `--disp-size-default-32' option to restore the default
     behaviour.

`--pcrel'
     Always keep branches PC-relative.  In the M680x0 architecture all
     branches are defined as PC-relative.  However, on some processors
     they are limited to word displacements maximum.  When `as' needs a
     long branch that is not available, it normally emits an absolute
     jump instead.  This option disables this substitution.  When this
     option is given and no long branches are available, only word
     branches will be emitted.  An error message will be generated if a
     word branch cannot reach its target.  This option has no effect on
     68020 and other processors that have long branches.  See Branch Improvement.

`-m68000'
     `as' can assemble code for several different members of the
     Motorola 680x0 family.  The default depends upon how `as' was
     configured when it was built; normally, the default is to assemble
     code for the 68020 microprocessor.  The following options may be
     used to change the default.  These options control which
     instructions and addressing modes are permitted.  The members of
     the 680x0 family are very similar.  For detailed information about
     the differences, see the Motorola manuals.

    `-m68000'
    `-m68ec000'
    `-m68hc000'
    `-m68hc001'
    `-m68008'
    `-m68302'
    `-m68306'
    `-m68307'
    `-m68322'
    `-m68356'
          Assemble for the 68000. `-m68008', `-m68302', and so on are
          synonyms for `-m68000', since the chips are the same from the
          point of view of the assembler.

    `-m68010'
          Assemble for the 68010.

    `-m68020'
    `-m68ec020'
          Assemble for the 68020.  This is normally the default.

    `-m68030'
    `-m68ec030'
          Assemble for the 68030.

    `-m68040'
    `-m68ec040'
          Assemble for the 68040.

    `-m68060'
    `-m68ec060'
          Assemble for the 68060.

    `-mcpu32'
    `-m68330'
    `-m68331'
    `-m68332'
    `-m68333'
    `-m68334'
    `-m68336'
    `-m68340'
    `-m68341'
    `-m68349'
    `-m68360'
          Assemble for the CPU32 family of chips.

    `-m5200'
          Assemble for the ColdFire family of chips.

    `-m68881'
    `-m68882'
          Assemble 68881 floating point instructions.  This is the
          default for the 68020, 68030, and the CPU32.  The 68040 and
          68060 always support floating point instructions.

    `-mno-68881'
          Do not assemble 68881 floating point instructions.  This is
          the default for 68000 and the 68010.  The 68040 and 68060
          always support floating point instructions, even if this
          option is used.

    `-m68851'
          Assemble 68851 MMU instructions.  This is the default for the
          68020, 68030, and 68060.  The 68040 accepts a somewhat
          different set of MMU instructions; `-m68851' and `-m68040'
          should not be used together.

    `-mno-68851'
          Do not assemble 68851 MMU instructions.  This is the default
          for the 68000, 68010, and the CPU32.  The 68040 accepts a
          somewhat different set of MMU instructions.