diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/conf/RENESAS7785LCR src-sh4a/sys/arch/evbsh3/conf/RENESAS7785LCR --- src-sh4a.orig/sys/arch/evbsh3/conf/RENESAS7785LCR 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/conf/RENESAS7785LCR 2010-04-06 22:55:22.000000000 +0900 @@ -12,33 +12,54 @@ #options INCLUDE_CONFIG_FILE # embed config file in kernel binary # Enable the hooks used for initializing the root memory-disk. -options MEMORY_DISK_HOOKS -options MEMORY_DISK_IS_ROOT # force root on memory disk -options MEMORY_DISK_SERVER=0 # no userspace memory disk support -options MEMORY_DISK_ROOT_SIZE=8192 # size of memory disk, in blocks -options MEMORY_DISK_RBFLAGS=RB_SINGLE # boot in single-user mode +#options MEMORY_DISK_HOOKS +#options MEMORY_DISK_IS_ROOT # force root on memory disk +#options MEMORY_DISK_SERVER=0 # no userspace memory disk support +#options MEMORY_DISK_ROOT_SIZE=8192 # size of memory disk, in blocks +#options MEMORY_DISK_RBFLAGS=RB_SINGLE # boot in single-user mode maxusers 32 # estimated number of users +makeoptions CPUFLAGS="-m4-nofpu" + # Board define -options RENESAS7785LCR +options RENESAS7785LCR # CPU support. -options SH4A +options SH4A options SH7785 -options SH4A_CPUMODE=16 -options SH4A_INPUT_CLOCK=33333333 # 33.333MHz (not PCLOCK) -options SH4A_EXT_ADDR32 # 32bit physical address mode. XXXnotyet -#options SH4A_EXT_MMU # TLB-extended mode. XXXnotyet. - -options DEBUG -options DDB # in-kernel debugger -options DIAGNOSTIC # cheap kernel consistency checks -options POOL_DIAGNOSTIC -options LOCKDEBUG # expensive locking checks/support -#options UVMHIST -#options UVMHIST_PRINT -options PGALLOC_VERBOSE +options SH4A_CPUMODE=16 +options SH4A_INPUT_CLOCK=33333333 # 33.333MHz (not PCLOCK) +#options SH4A_EXT_ADDR32 # 32bit physical address mode. XXXnotyet +#options SH4A_EXT_MMU # TLB-extended mode. XXXnotyet. + +# Standard system options + +options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT +#options HZ=100 +options NTP # NTP phase/frequency locked loop + +options KTRACE # system call tracing via ktrace(1) + +options SYSVMSG # System V-like message queues +options SYSVSEM # System V-like semaphores +options SYSVSHM # System V-like memory sharing + +options USERCONF # userconf(4) support +#options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel + +# Development and Debugging options +#options DIAGNOSTIC # cheap kernel consistency checks +#options DEBUG +#options DDB # in-kernel debugger +#options POOL_DIAGNOSTIC +#options LOCKDEBUG # expensive locking checks/support +#options UVMHIST +#options UVMHIST_PRINT +#options PGALLOC_VERBOSE +#options KSTACK_DEBUG +#options DEBUG_EXEC +options SYMTAB_SPACE=512000 # 0x09000000 - 0x1000 options IOM_RAM_BEGIN=0x08fff000 # Specify VBR address only. @@ -48,6 +69,7 @@ #options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel # Compatibility options +options COMPAT_50 # NetBSD 5.0 options COMPAT_43 # and 4.3BSD options COMPAT_BSDPTY # /dev/[pt]ty?? ptys. @@ -56,12 +78,23 @@ # File systems file-system FFS # UFS +file-system NFS # NFS +file-system PTYFS # /dev/ptm support +file-system PROCFS # /proc +file-system TMPFS # Efficient memory file-system + options FFS_NO_SNAPSHOT # No FFS snapshot support options WAPBL # File system journaling support - Experimental +# Networking options +options INET # IP + ICMP + TCP + UDP +options INET6 # IPV6 + # Kernel root file system and dump configuration. config netbsd root on ? type ? +options NFS_BOOT_DHCP,NFS_BOOT_BOOTPARAM + # # Device configuration # @@ -71,7 +104,34 @@ options SCIFCONSOLE,SCIFCN_SPEED=115200 scif0 at shb? +# PCI bus support +#options PCIVERBOSE # verbose PCI device autoconfig messages +#options PCI_CONFIG_DUMP # verbosely dump PCI config space +options PCI_NETBSD_CONFIGURE +shpcic* at mainbus? # SH7785 PCIC +pci0 at shpcic? bus ? + +re* at pci? dev ? function ? # Realtek 8139C+/8169/8169S/8110S +rgephy* at mii? phy ? # Realtek 8169S/8110S internal PHYs + +satalink* at pci? dev ? function ? # SiI SATALink controllers +atabus* at ata? +wd* at atabus? drive ? flags 0x0000 + + # Pseudo-Devices pseudo-device md 1 # memory disk device (ramdisk) + +pseudo-device vnd # disk-like interface to files +options VND_COMPRESSION # compressed vnd(4) + +# network pseudo-devices +pseudo-device bpfilter # Berkeley packet filter +pseudo-device ipfilter # IP filter (firewall) and NAT +pseudo-device loop # network loopback + +# miscellaneous pseudo-devices pseudo-device pty # pseudo-terminals +pseudo-device rnd # /dev/random and in-kernel generator pseudo-device clockctl # user control of clock subsystem +pseudo-device ksyms # /dev/ksyms diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/conf/files.evbsh3 src-sh4a/sys/arch/evbsh3/conf/files.evbsh3 --- src-sh4a.orig/sys/arch/evbsh3/conf/files.evbsh3 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/conf/files.evbsh3 2010-03-30 19:50:10.000000000 +0900 @@ -12,6 +12,7 @@ file arch/evbsh3/evbsh3/machdep.c sh3 | sh4 file arch/evbsh3/evbsh3/autoconf.c file arch/evbsh3/evbsh3/clock_machdep.c +file arch/evbsh3/evbsh3/bus_dma.c file arch/sh3/sh3/disksubr.c disk file arch/evbsh3/renesas7785lcr/machdep.c renesas7785lcr @@ -35,6 +36,11 @@ include "dev/ata/files.ata" +# +# Machine-independent I2O drivers +# +include "dev/i2o/files.i2o" + # Memory Disk for install floppy file dev/md_root.c memory_disk_hooks @@ -43,7 +49,7 @@ # define mainbus { } -device mainbus: mainbus +device mainbus: mainbus, pcibus attach mainbus at root file arch/evbsh3/evbsh3/mainbus.c mainbus @@ -53,4 +59,12 @@ include "arch/sh3/conf/files.shb" +# +# PCI bus +# +include "dev/pci/files.pci" +include "arch/sh3/conf/files.shpcic" + +file arch/evbsh3/renesas7785lcr/shpcic_machdep.c renesas7785lcr & pci + include "arch/evbsh3/conf/majors.evbsh3" diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/conf/majors.evbsh3 src-sh4a/sys/arch/evbsh3/conf/majors.evbsh3 --- src-sh4a.orig/sys/arch/evbsh3/conf/majors.evbsh3 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/conf/majors.evbsh3 2010-03-29 20:21:34.000000000 +0900 @@ -1,49 +1,51 @@ -# $NetBSD: majors.hpcsh,v 1.22 2008/11/12 12:36:01 ad Exp $ +# $NetBSD: majors.evbsh3,v 1.18 2008/11/12 12:36:00 ad Exp $ # -# Device majors for hpcsh +# Device majors for evbsh3 # -device-major mem char 0 -device-major swap char 1 block 0 vmswap -device-major cons char 2 -device-major ctty char 3 -device-major filedesc char 4 -device-major log char 5 +device-major cons char 0 +device-major ctty char 1 +device-major mem char 2 +device-major wd char 3 block 0 wd +device-major swap char 4 block 1 vmswap +device-major pts char 5 pty device-major ptc char 6 pty -device-major pts char 7 pty +device-major log char 7 device-major com char 8 com -device-major wd char 10 block 1 wd +device-major scif char 10 scif +device-major sci char 11 sci -device-major md char 12 block 6 md -device-major ccd char 13 block 7 ccd -device-major vnd char 14 block 8 vnd -device-major raid char 15 block 9 raid -device-major scsibus char 16 scsibus -device-major sd char 17 block 3 sd -device-major st char 18 block 4 st -device-major cd char 19 block 5 cd -device-major ch char 20 ch -device-major uk char 21 uk -device-major ss char 22 ss -device-major ipl char 23 ipfilter -device-major tun char 24 tun -device-major bpf char 25 bpfilter -device-major wsdisplay char 26 wsdisplay -device-major wskbd char 27 wskbd -device-major wsmouse char 28 wsmouse -device-major wsmux char 29 wsmux -device-major rnd char 30 rnd -device-major scif char 31 scif -device-major sci char 32 sci -device-major biconsdev char 33 biconsdev -device-major clockctl char 34 clockctl -device-major cgd char 36 block 10 cgd -device-major ksyms char 37 ksyms -device-major wsfont char 39 wsfont -device-major apmdev char 40 apmdev +device-major sd char 13 block 4 sd +device-major st char 14 block 5 st +device-major cd char 15 block 6 cd + +device-major ch char 17 ch +device-major ccd char 18 block 16 ccd +device-major ss char 19 ss +device-major uk char 20 uk + +device-major filedesc char 22 +device-major bpf char 23 bpfilter +device-major md char 24 block 17 md + + +device-major tun char 40 tun +device-major vnd char 41 block 14 vnd device-major audio char 42 audio +device-major ipl char 44 ipfilter + +device-major rnd char 46 rnd +device-major vcoda char 47 vcoda +device-major scsibus char 48 scsibus +device-major raid char 49 block 18 raid +device-major esh char 50 esh +device-major wdog char 51 wdog +device-major clockctl char 52 clockctl +device-major cgd char 54 block 19 cgd +device-major ksyms char 55 ksyms + device-major nsmb char 98 nsmb # Majors up to 143 are reserved for machine-dependant drivers. diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/evbsh3/bus_dma.c src-sh4a/sys/arch/evbsh3/evbsh3/bus_dma.c --- src-sh4a.orig/sys/arch/evbsh3/evbsh3/bus_dma.c 1970-01-01 09:00:00.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/evbsh3/bus_dma.c 2010-03-30 19:49:39.000000000 +0900 @@ -0,0 +1,777 @@ +/* $NetBSD$ */ + +/* + * Copyright (c) 2005, 2010 NONAKA Kimihiro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#define _EVBSH3_BUS_DMA_PRIVATE +#include + +#if defined(BUSDMA_DEBUG) +int busdma_debug = 1; +#define DPRINTF(a) if (busdma_debug) printf a +#else +#define DPRINTF(a) +#endif + +struct _bus_dma_tag evbsh3_bus_dma = { + ._cookie = NULL, + + ._dmamap_create = _bus_dmamap_create, + ._dmamap_destroy = _bus_dmamap_destroy, + ._dmamap_load = _bus_dmamap_load, + ._dmamap_load_mbuf = _bus_dmamap_load_mbuf, + ._dmamap_load_uio = _bus_dmamap_load_uio, + ._dmamap_load_raw = _bus_dmamap_load_raw, + ._dmamap_unload = _bus_dmamap_unload, + ._dmamap_sync = _bus_dmamap_sync, + + ._dmamem_alloc = _bus_dmamem_alloc, + ._dmamem_free = _bus_dmamem_free, + ._dmamem_map = _bus_dmamem_map, + ._dmamem_unmap = _bus_dmamem_unmap, + ._dmamem_mmap = _bus_dmamem_mmap, +}; + +/* + * Create a DMA map. + */ +int +_bus_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, + bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) +{ + bus_dmamap_t map; + void *mapstore; + size_t mapsize; + + DPRINTF(("%s: t = %p, size = %ld, nsegments = %d, maxsegsz = %ld," + " boundary = %ld, flags = %x\n", + __func__, t, size, nsegments, maxsegsz, boundary, flags)); + + /* + * Allocate and initialize the DMA map. The end of the map is + * a variable-sized array of segments, so we allocate enough + * room for them in one shot. bus_dmamap_t includes one + * bus_dma_segment_t already, hence the (nsegments - 1). + * + * Note that we don't preserve WAITOK and NOWAIT flags. + * Preservation of ALLOCNOW notifies others that we've + * reserved these resources, and they are not to be freed. + */ + mapsize = sizeof(struct _bus_dmamap) + + (sizeof(bus_dma_segment_t) * (nsegments - 1)); + mapstore = malloc(mapsize, M_DMAMAP, M_ZERO + | ((flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK)); + if (mapstore == NULL) + return ENOMEM; + + DPRINTF(("%s: dmamp = %p\n", __func__, mapstore)); + + map = (bus_dmamap_t)mapstore; + map->_dm_size = size; + map->_dm_segcnt = nsegments; + map->_dm_maxsegsz = maxsegsz; + map->_dm_boundary = boundary; + map->_dm_flags = flags & ~(BUS_DMA_WAITOK | BUS_DMA_NOWAIT); + + map->dm_mapsize = 0; /* no valid mappings */ + map->dm_nsegs = 0; + + *dmamp = map; + return 0; +} + +/* + * Destroy a DMA map. + */ +void +_bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t map) +{ + + DPRINTF(("%s: t = %p, map = %p\n", __func__, t, map)); + + free(map, M_DMAMAP); +} + +static inline int +_bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map, + paddr_t paddr, vaddr_t vaddr, int size, int *segp, paddr_t *lastaddrp, + int first) +{ + bus_dma_segment_t * const segs = map->dm_segs; + bus_addr_t bmask = ~(map->_dm_boundary - 1); + bus_addr_t lastaddr; + int nseg; + int sgsize; + + nseg = *segp; + lastaddr = *lastaddrp; + + DPRINTF(("%s: t = %p, map = %p, paddr = 0x%08lx," + " vaddr = 0x%08lx, size = %d\n", + __func__, t, map, paddr, vaddr, size)); + DPRINTF(("%s: nseg = %d, bmask = 0x%08lx, lastaddr = 0x%08lx\n", + __func__, nseg, bmask, lastaddr)); + + do { + sgsize = size; + + /* + * Make sure we don't cross any boundaries. + */ + if (map->_dm_boundary > 0) { + bus_addr_t baddr; /* next boundary address */ + + baddr = (paddr + map->_dm_boundary) & bmask; + if (sgsize > (baddr - paddr)) + sgsize = (baddr - paddr); + } + + DPRINTF(("%s: sgsize = %d\n", __func__, sgsize)); + + /* + * Insert chunk coalescing with previous segment if possible. + */ + if (first) { + DPRINTF(("%s: first\n", __func__)); + first = 0; + +#if !defined(SH4A_EXT_ADDR32) + segs[nseg].ds_addr = SH3_PHYS_TO_P2SEG(paddr); +#else + segs[nseg].ds_addr = paddr; +#endif + segs[nseg].ds_len = sgsize; + segs[nseg]._ds_vaddr = vaddr; + } + else if ((paddr == lastaddr) + && (segs[nseg].ds_len + sgsize <= map->_dm_maxsegsz) + && (map->_dm_boundary == 0 || + (segs[nseg].ds_addr & bmask) == (paddr & bmask))) + { + DPRINTF(("%s: coalesce\n", __func__)); + + segs[nseg].ds_len += sgsize; + } + else { + DPRINTF(("%s: new\n", __func__)); + + ++nseg; + if (nseg >= map->_dm_segcnt) + break; + +#if !defined(SH4A_EXT_ADDR32) + segs[nseg].ds_addr = SH3_PHYS_TO_P2SEG(paddr); +#else + segs[nseg].ds_addr = paddr; +#endif + segs[nseg].ds_len = sgsize; + segs[nseg]._ds_vaddr = vaddr; + } + + paddr += sgsize; + vaddr += sgsize; + size -= sgsize; + lastaddr = paddr; + + DPRINTF(("%s: lastaddr = 0x%08lx, paddr = 0x%08lx," + " vaddr = 0x%08lx, size = %d\n", + __func__, lastaddr, paddr, vaddr, size)); + } while (size > 0); + + DPRINTF(("%s: nseg = %d\n", __func__, nseg)); + + *segp = nseg; + *lastaddrp = lastaddr; + + if (size != 0) { + /* + * It didn't fit. If there is a chained window, we + * will automatically fall back to it. + */ + return EFBIG; /* XXX better return value here? */ + } + + return 0; +} + +static inline int +_bus_bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf, + bus_size_t buflen, struct proc *p, int flags, int *segp) +{ + bus_size_t sgsize; + bus_addr_t curaddr; + bus_size_t len; + paddr_t lastaddr; + vaddr_t vaddr = (vaddr_t)buf; + pmap_t pmap; + int first; + int error; + + DPRINTF(("%s: t = %p, map = %p, buf = %p, buflen = %ld," + " p = %p, flags = %x\n", + __func__, t, map, buf, buflen, p, flags)); + + if (p != NULL) + pmap = p->p_vmspace->vm_map.pmap; + else + pmap = pmap_kernel(); + + first = 1; + lastaddr = 0; + + len = buflen; + while (len > 0) { + bool mapped; + + mapped = pmap_extract(pmap, vaddr, &curaddr); + if (!mapped) + return EFAULT; +#if defined(SH4A_EXT_ADDR32) // XXXNONAKA + if (curaddr < 0x20000000) + curaddr |= 0x40000000; +#endif + sgsize = PAGE_SIZE - (vaddr & PGOFSET); + if (len < sgsize) + sgsize = len; + + error = _bus_dmamap_load_paddr(t, map, curaddr, vaddr, sgsize, + segp, &lastaddr, first); + if (error) + return error; + + vaddr += sgsize; + len -= sgsize; + first = 0; + } + + return 0; +} + +/* + * Load a DMA map with a linear buffer. + */ +int +_bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf, + bus_size_t buflen, struct proc *p, int flags) +{ +#if !defined(SH4A_EXT_ADDR32) + bus_addr_t addr = (bus_addr_t)buf; +#endif + int seg; + int error; + + DPRINTF(("%s: t = %p, map = %p, buf = %p, buflen = %ld," + " p = %p, flags = %x\n", + __func__, t, map, buf, buflen, p, flags)); + + /* make sure that on error condition we return "no valid mappings" */ + map->dm_mapsize = 0; + map->dm_nsegs = 0; + + if (buflen > map->_dm_size) + return EINVAL; + + error = 0; + seg = 0; + +#if !defined(SH4A_EXT_ADDR32) + if (SH3_P1SEG_BASE <= addr && addr + buflen <= SH3_P2SEG_END) { + bus_addr_t curaddr; + bus_size_t sgsize; + bus_size_t len = buflen; + paddr_t lastaddr; + int first; + + DPRINTF(("%s: P[12]SEG (0x%08lx)\n", __func__, addr)); + + first = 1; + lastaddr = 0; + + while (len > 0) { + curaddr = SH3_P1SEG_TO_PHYS(addr); + + sgsize = PAGE_SIZE - ((u_long)addr & PGOFSET); + if (len < sgsize) + sgsize = len; + + error = _bus_dmamap_load_paddr(t, map, + curaddr, addr, sgsize, + &seg, &lastaddr, first); + if (error) + break; + + addr += sgsize; + len -= sgsize; + first = 0; + } + } else +#endif + { + error = _bus_bus_dmamap_load_buffer(t, map, buf, buflen, + p, flags, &seg); + } + if (error) + return error; + + map->dm_nsegs = seg + 1; + map->dm_mapsize = buflen; + return 0; +} + +/* + * Like _bus_dmamap_load(), but for mbufs. + */ +int +_bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0, + int flags) +{ + struct mbuf *m; + paddr_t lastaddr; + int seg; + int first; + int error; + + DPRINTF(("%s: t = %p, map = %p, m0 = %p, flags = %x\n", + __func__, t, map, m0, flags)); + + /* make sure that on error condition we return "no valid mappings" */ + map->dm_nsegs = 0; + map->dm_mapsize = 0; + +#ifdef DIAGNOSTIC + if ((m0->m_flags & M_PKTHDR) == 0) + panic("_bus_dmamap_load_mbuf: no packet header"); +#endif + + if (m0->m_pkthdr.len > map->_dm_size) + return EINVAL; + + seg = 0; + first = 1; + lastaddr = 0; + + for (m = m0; m != NULL; m = m->m_next) { + paddr_t paddr; + vaddr_t vaddr; + int size; + + if (m->m_len == 0) + continue; + + vaddr = (vaddr_t)m->m_data; + size = m->m_len; + +#if !defined(SH4A_EXT_ADDR32) + if (SH3_P1SEG_BASE <= vaddr && vaddr < SH3_P3SEG_BASE) { + paddr = (paddr_t)(PMAP_UNMAP_POOLPAGE(vaddr)); + error = _bus_dmamap_load_paddr(t, map, + paddr, vaddr, size, + &seg, &lastaddr, first); + if (error) + return error; + first = 0; + } else +#endif + { + /* XXX: stolen from load_buffer, need to refactor */ + while (size > 0) { + bus_size_t sgsize; + bool mapped; + + mapped = pmap_extract(pmap_kernel(), vaddr, + &paddr); + if (!mapped) + return EFAULT; +#if defined(SH4A_EXT_ADDR32) // XXXNONAKA + if (paddr < 0x20000000) + paddr |= 0x40000000; +#endif + + sgsize = PAGE_SIZE - (vaddr & PGOFSET); + if (size < sgsize) + sgsize = size; + + error = _bus_dmamap_load_paddr(t, map, + paddr, vaddr, sgsize, + &seg, &lastaddr, first); + if (error) + return error; + + vaddr += sgsize; + size -= sgsize; + first = 0; + } + + } + } + + map->dm_nsegs = seg + 1; + map->dm_mapsize = m0->m_pkthdr.len; + return 0; +} + +/* + * Like _bus_dmamap_load(), but for uios. + */ +int +_bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio, + int flags) +{ + + panic("_bus_dmamap_load_uio: not implemented"); +} + +/* + * Like _bus_dmamap_load(), but for raw memory allocated with + * bus_dmamem_alloc(). + */ +int +_bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, + bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags) +{ + + panic("_bus_dmamap_load_raw: not implemented"); +} + +/* + * Unload a DMA map. + */ +void +_bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) +{ + + DPRINTF(("%s: t = %p, map = %p\n", __func__, t, map)); + + map->dm_nsegs = 0; + map->dm_mapsize = 0; +} + +/* + * Synchronize a DMA map. + */ +void +_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, + bus_size_t len, int ops) +{ + bus_size_t minlen; + bus_addr_t addr, naddr; + int i; + + DPRINTF(("%s: t = %p, map = %p, offset = %ld, len = %ld, ops = %x\n", + __func__, t, map, offset, len, ops)); + +#ifdef DIAGNOSTIC + if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 && + (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0) + panic("_bus_dmamap_sync: mix PRE and POST"); + + if (offset >= map->dm_mapsize) + panic("_bus_dmamap_sync: bad offset"); + if ((offset + len) > map->dm_mapsize) + panic("_bus_dmamap_sync: bad length"); +#endif + + if (!sh_cache_enable_dcache) { + /* Nothing to do */ + DPRINTF(("%s: disabled D-Cache\n", __func__)); + return; + } + + for (i = 0; i < map->dm_nsegs && len != 0; i++) { + /* Find the beginning segment. */ + if (offset >= map->dm_segs[i].ds_len) { + offset -= map->dm_segs[i].ds_len; + continue; + } + + /* + * Now at the first segment to sync; nail + * each segment until we have exhausted the + * length. + */ + minlen = len < map->dm_segs[i].ds_len - offset ? + len : map->dm_segs[i].ds_len - offset; + + addr = map->dm_segs[i]._ds_vaddr; + naddr = addr + offset; + +#if !defined(SH4A_EXT_ADDR32) + if ((naddr >= SH3_P2SEG_BASE) + && (naddr + minlen <= SH3_P2SEG_END)) { + DPRINTF(("%s: P2SEG (0x%08lx)\n", __func__, naddr)); + offset = 0; + len -= minlen; + continue; + } +#endif + + DPRINTF(("%s: flushing segment %d " + "(0x%lx+%lx, 0x%lx+0x%lx) (remain = %ld)\n", + __func__, i, + addr, offset, addr, offset + minlen - 1, len)); + + switch (ops) { + case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE: + if (SH_HAS_WRITEBACK_CACHE) + sh_dcache_wbinv_range(naddr, minlen); + else + sh_dcache_inv_range(naddr, minlen); + break; + + case BUS_DMASYNC_PREREAD: + if (SH_HAS_WRITEBACK_CACHE && + ((naddr | minlen) & (sh_cache_line_size - 1)) != 0) + sh_dcache_wbinv_range(naddr, minlen); + else + sh_dcache_inv_range(naddr, minlen); + break; + + case BUS_DMASYNC_PREWRITE: + if (SH_HAS_WRITEBACK_CACHE) + sh_dcache_wb_range(naddr, minlen); + break; + + case BUS_DMASYNC_POSTREAD: + case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE: + sh_dcache_inv_range(naddr, minlen); + break; + } + offset = 0; + len -= minlen; + } +} + +/* + * Allocate memory safe for DMA. + */ +int +_bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, + bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs, + int flags) +{ + extern paddr_t avail_start, avail_end; /* from pmap.c */ + struct pglist mlist; + paddr_t curaddr, lastaddr; + struct vm_page *m; + int curseg, error; + + DPRINTF(("%s: t = %p, size = %ld, alignment = %ld, boundary = %ld," + " segs = %p, nsegs = %d, rsegs = %p, flags = %x\n", + __func__, t, size, alignment, boundary, + segs, nsegs, rsegs, flags)); + DPRINTF(("%s: avail_start = 0x%08lx, avail_end = 0x%08lx\n", + __func__, avail_start, avail_end)); + + /* Always round the size. */ + size = round_page(size); + + /* + * Allocate the pages from the VM system. + */ + error = uvm_pglistalloc(size, avail_start, avail_end - PAGE_SIZE, + alignment, boundary, &mlist, nsegs, (flags & BUS_DMA_NOWAIT) == 0); + if (error) + return error; + + /* + * Compute the location, size, and number of segments actually + * returned by the VM code. + */ + m = mlist.tqh_first; + curseg = 0; + lastaddr = segs[curseg].ds_addr = VM_PAGE_TO_PHYS(m); + segs[curseg].ds_len = PAGE_SIZE; + + DPRINTF(("%s: m = %p, lastaddr = 0x%08lx\n", __func__, m, lastaddr)); + + while ((m = TAILQ_NEXT(m, pageq.queue)) != NULL) { + curaddr = VM_PAGE_TO_PHYS(m); + DPRINTF(("%s: m = %p, curaddr = 0x%08lx, lastaddr = 0x%08lx\n", + __func__, m, curaddr, lastaddr)); + + if (curaddr == (lastaddr + PAGE_SIZE)) { + segs[curseg].ds_len += PAGE_SIZE; + } else { + DPRINTF(("%s: new segment\n", __func__)); + curseg++; + segs[curseg].ds_addr = curaddr; + segs[curseg].ds_len = PAGE_SIZE; + } + lastaddr = curaddr; + } + + *rsegs = curseg + 1; + + DPRINTF(("%s: curseg = %d, *rsegs = %d\n", __func__, curseg, *rsegs)); + + return 0; +} + +/* + * Common function for freeing DMA-safe memory. May be called by + * bus-specific DMA memory free functions. + */ +void +_bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs) +{ + struct vm_page *m; + bus_addr_t addr; + struct pglist mlist; + int curseg; + + DPRINTF(("%s: t = %p, segs = %p, nsegs = %d\n", + __func__, t, segs, nsegs)); + + /* + * Build a list of pages to free back to the VM system. + */ + TAILQ_INIT(&mlist); + for (curseg = 0; curseg < nsegs; curseg++) { + DPRINTF(("%s: segs[%d]: ds_addr = 0x%08lx, ds_len = %ld\n", + __func__, curseg, + segs[curseg].ds_addr, segs[curseg].ds_len)); + + for (addr = segs[curseg].ds_addr; + addr < (segs[curseg].ds_addr + segs[curseg].ds_len); + addr += PAGE_SIZE) + { + m = PHYS_TO_VM_PAGE(addr); + DPRINTF(("%s: m = %p\n", __func__, m)); + TAILQ_INSERT_TAIL(&mlist, m, pageq.queue); + } + } + + uvm_pglistfree(&mlist); +} + + +int +_bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, + size_t size, void **kvap, int flags) +{ + vaddr_t va, topva; + bus_addr_t addr; + int curseg; + + DPRINTF(("%s: t = %p, segs = %p, nsegs = %d, size = %d," + " kvap = %p, flags = %x\n", + __func__, t, segs, nsegs, size, kvap, flags)); + +#if !defined(SH4A_EXT_ADDR32) + /* + * If we're mapping only a single segment, use direct-mapped + * va, to avoid thrashing the TLB. + */ + if (nsegs == 1) { + if (flags & BUS_DMA_COHERENT) + *kvap = (void *)SH3_PHYS_TO_P2SEG(segs[0].ds_addr); + else + *kvap = (void *)SH3_PHYS_TO_P1SEG(segs[0].ds_addr); + + DPRINTF(("%s: addr = 0x%08lx, kva = %p\n", + __func__, segs[0].ds_addr, *kvap)); + return 0; + } +#endif + + /* Always round the size. */ + size = round_page(size); + + va = uvm_km_alloc(kernel_map, size, 0, + UVM_KMF_VAONLY | ((flags & BUS_DMA_NOWAIT) ? UVM_KMF_NOWAIT : 0)); + if (va == 0) + return ENOMEM; + topva = va; + + for (curseg = 0; curseg < nsegs; curseg++) { + DPRINTF(("%s: segs[%d]: ds_addr = 0x%08lx, ds_len = %ld\n", + __func__, curseg, + segs[curseg].ds_addr, segs[curseg].ds_len)); + + for (addr = segs[curseg].ds_addr; + addr < segs[curseg].ds_addr + segs[curseg].ds_len; + addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) + { + if (__predict_false(size == 0)) + panic("_bus_dmamem_map: size botch"); + + pmap_kenter_pa(va, addr, + VM_PROT_READ | VM_PROT_WRITE, 0); + } + } + + pmap_update(pmap_kernel()); + *kvap = (void *)topva; + return 0; +} + +void +_bus_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size) +{ + vaddr_t vaddr = (vaddr_t)kva; + + DPRINTF(("%s: t = %p, kva = %p, size = %d\n", + __func__, t, kva, size)); + +#ifdef DIAGNOSTIC + if (vaddr & PAGE_MASK) + panic("_bus_dmamem_unmap"); +#endif + +#if !defined(SH4A_EXT_ADDR32) + /* nothing to do if we mapped it via P1SEG or P2SEG */ + if (SH3_P1SEG_BASE <= vaddr && vaddr <= SH3_P2SEG_END) + return; +#endif + + size = round_page(size); + pmap_kremove(vaddr, size); + pmap_update(pmap_kernel()); + uvm_km_free(kernel_map, vaddr, size, UVM_KMF_VAONLY); +} + +paddr_t +_bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, + off_t off, int prot, int flags) +{ + + /* Not implemented. */ + return (paddr_t)-1; +} diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/evbsh3/mainbus.c src-sh4a/sys/arch/evbsh3/evbsh3/mainbus.c --- src-sh4a.orig/sys/arch/evbsh3/evbsh3/mainbus.c 2008-04-29 11:38:26.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/evbsh3/mainbus.c 2010-01-14 16:16:51.000000000 +0900 @@ -29,6 +29,8 @@ #include __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.7 2008/04/28 20:23:18 martin Exp $"); +#include "pci.h" + #include #include #include @@ -38,12 +40,6 @@ void mainbus_attach(struct device *, struct device *, void *); int mainbus_print(void *, const char *); -struct mainbus_attach_args mainbusdevs[] = { - { "cpu" }, - { "shb" }, - { NULL } /* terminator */ -}; - CFATTACH_DECL(mainbus, sizeof(struct device), mainbus_match, mainbus_attach, NULL, NULL); @@ -57,12 +53,26 @@ void mainbus_attach(struct device *parent, struct device *self, void *aux) { - struct mainbus_attach_args *ma; + struct mainbus_attach_args mba; printf("\n"); - for (ma = mainbusdevs; ma->ma_name != NULL; ma++) - config_found(self, ma, mainbus_print); + /* CPU */ + memset(&mba, 0, sizeof(mba)); + mba.ma_name = "cpu"; + config_found(self, &mba, mainbus_print); + + /* SH bus */ + memset(&mba, 0, sizeof(mba)); + mba.ma_name = "shb"; + config_found(self, &mba, mainbus_print); + +#if NPCI > 0 + /* SH PCIC */ + memset(&mba, 0, sizeof(mba)); + mba.ma_name = "shpcic"; + config_found(self, &mba, mainbus_print); +#endif } int diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/include/bus.h src-sh4a/sys/arch/evbsh3/include/bus.h --- src-sh4a.orig/sys/arch/evbsh3/include/bus.h 1999-09-13 19:30:29.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/include/bus.h 2010-01-14 15:08:40.000000000 +0900 @@ -1,7 +1,717 @@ /* $NetBSD: bus.h,v 1.1 1999/09/13 10:30:29 itojun Exp $ */ + +/*- + * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef _EVBSH3_BUS_H_ -#define _EVBSH3_BUS_H_ +#define _EVBSH3_BUS_H_ + +#include + +#ifdef _KERNEL +/* + * Turn on BUS_SPACE_DEBUG if the global DEBUG option is enabled. + */ +#if defined(DEBUG) && !defined(BUS_SPACE_DEBUG) +#define BUS_SPACE_DEBUG +#endif + +#ifdef BUS_SPACE_DEBUG +#include /* for printf() prototype */ +/* + * Macros for checking the aligned-ness of pointers passed to bus + * space ops. Strict alignment is required by the Alpha architecture, + * and a trap will occur if unaligned access is performed. These + * may aid in the debugging of a broken device driver by displaying + * useful information about the problem. + */ +#define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ + ((((u_long)(p)) & (sizeof(t)-1)) == 0) + +#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ +({ \ + if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ + printf("%s 0x%lx not aligned to %lu bytes %s:%d\n", \ + d, (u_long)(p), (u_long)sizeof(t), __FILE__, __LINE__); \ + } \ + (void) 0; \ +}) + +#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) +#else +#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0 +#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) +#endif /* BUS_SPACE_DEBUG */ +#endif /* _KERNEL */ + +typedef u_long bus_addr_t; +typedef u_long bus_size_t; + +typedef struct _bus_space *bus_space_tag_t; +typedef u_long bus_space_handle_t; + +struct _bus_space { + /* cookie */ + void *bs_cookie; + + /* mapping/unmapping */ + int (*bs_map)(void *, bus_addr_t, bus_size_t, + int, bus_space_handle_t *); + void (*bs_unmap)(void *, bus_space_handle_t, + bus_size_t); + int (*bs_subregion)(void *, bus_space_handle_t, + bus_size_t, bus_size_t, bus_space_handle_t *); + + /* allocation/deallocation */ + int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, + bus_size_t, bus_size_t, bus_size_t, int, + bus_addr_t *, bus_space_handle_t *); + void (*bs_free)(void *, bus_space_handle_t, + bus_size_t); + + /* get kernel virtual address */ + void * (*bs_vaddr)(void *, bus_space_handle_t); + + /* mmap bus space for user */ + paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); + + /* read (single) */ + uint8_t (*bs_r_1)(void *, bus_space_handle_t, + bus_size_t); + uint16_t (*bs_r_2)(void *, bus_space_handle_t, + bus_size_t); + uint32_t (*bs_r_4)(void *, bus_space_handle_t, + bus_size_t); + uint64_t (*bs_r_8)(void *, bus_space_handle_t, + bus_size_t); + + /* read multiple */ + void (*bs_rm_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rm_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rm_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rm_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* read region */ + void (*bs_rr_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rr_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rr_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rr_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* read stream (single) */ + uint8_t (*bs_rs_1)(void *, bus_space_handle_t, + bus_size_t); + uint16_t (*bs_rs_2)(void *, bus_space_handle_t, + bus_size_t); + uint32_t (*bs_rs_4)(void *, bus_space_handle_t, + bus_size_t); + uint64_t (*bs_rs_8)(void *, bus_space_handle_t, + bus_size_t); + + /* read multiple stream */ + void (*bs_rms_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rms_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rms_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rms_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* read region stream */ + void (*bs_rrs_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rrs_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rrs_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rrs_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); + + /* write (single) */ + void (*bs_w_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t); + void (*bs_w_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t); + void (*bs_w_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t); + void (*bs_w_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t); + + /* write multiple */ + void (*bs_wm_1)(void *, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wm_2)(void *, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wm_4)(void *, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wm_8)(void *, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* write region */ + void (*bs_wr_1)(void *, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wr_2)(void *, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wr_4)(void *, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wr_8)(void *, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* write stream (single) */ + void (*bs_ws_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t); + void (*bs_ws_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t); + void (*bs_ws_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t); + void (*bs_ws_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t); + + /* write multiple stream */ + void (*bs_wms_1)(void *, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wms_2)(void *, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wms_4)(void *, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wms_8)(void *, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* write region stream */ + void (*bs_wrs_1)(void *, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wrs_2)(void *, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wrs_4)(void *, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wrs_8)(void *, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); + + /* set multiple */ + void (*bs_sm_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t, bus_size_t); + void (*bs_sm_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t, bus_size_t); + void (*bs_sm_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t, bus_size_t); + void (*bs_sm_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t, bus_size_t); + + /* set region */ + void (*bs_sr_1)(void *, bus_space_handle_t, + bus_size_t, uint8_t, bus_size_t); + void (*bs_sr_2)(void *, bus_space_handle_t, + bus_size_t, uint16_t, bus_size_t); + void (*bs_sr_4)(void *, bus_space_handle_t, + bus_size_t, uint32_t, bus_size_t); + void (*bs_sr_8)(void *, bus_space_handle_t, + bus_size_t, uint64_t, bus_size_t); + + /* copy */ + void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); +}; + +#ifdef _KERNEL + +extern struct _bus_space evbsh3_bus_space; + +/* + * Utility macros; INTERNAL USE ONLY. + */ +#define __bs_c(a,b) __CONCAT(a,b) +#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) + +#define __bs_rs(sz, tn, t, h, o) \ + (__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"), \ + (*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o)) +#define __bs_rss(sz, tn, t, h, o) \ + (__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"), \ + (*(t)->__bs_opname(rs,sz))((t)->bs_cookie, h, o)) + +#define __bs_ws(sz, tn, t, h, o, v) \ +do { \ + __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ + (*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v); \ +} while (0) +#define __bs_wss(sz, tn, t, h, o, v) \ +do { \ + __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ + (*(t)->__bs_opname(ws,sz))((t)->bs_cookie, h, o, v); \ +} while (0) + +#define __bs_nonsingle(type, sz, tn, t, h, o, a, c) \ +do { \ + __BUS_SPACE_ADDRESS_SANITY((a), tn, "buffer"); \ + __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ + (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c); \ +} while (0) + +#define __bs_set(type, sz, tn, t, h, o, v, c) \ +do { \ + __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ + (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c); \ +} while (0) + +#define __bs_copy(sz, tn, t, h1, o1, h2, o2, cnt) \ +do { \ + __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), tn, "bus addr 1"); \ + __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), tn, "bus addr 2"); \ + (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt); \ +} while (0) + + +/* + * Mapping and unmapping operations. + */ +#define bus_space_map(t, a, s, f, hp) \ + (*(t)->bs_map)((t)->bs_cookie, (a), (s), (f), (hp)) +#define bus_space_unmap(t, h, s) \ + (*(t)->bs_unmap)((t)->bs_cookie, (h), (s)) +#define bus_space_subregion(t, h, o, s, hp) \ + (*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp)) + +#endif /* _KERNEL */ + +#define BUS_SPACE_MAP_CACHEABLE 0x01 +#define BUS_SPACE_MAP_LINEAR 0x02 +#define BUS_SPACE_MAP_PREFETCHABLE 0x04 + +#ifdef _KERNEL +/* + * Allocation and deallocation operations. + */ +#define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \ + (*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \ + (f), (ap), (hp)) +#define bus_space_free(t, h, s) \ + (*(t)->bs_free)((t)->bs_cookie, (h), (s)) + +/* + * Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR. + */ +#define bus_space_vaddr(t, h) \ + (*(t)->bs_vaddr)((t)->bs_cookie, (h)) + +/* + * MMap bus space for a user application. + */ +#define bus_space_mmap(t, a, o, p, f) \ + (*(t)->bs_mmap)((t)->bs_cookie, (a), (o), (p), (f)) + +/* + * Bus barrier operations. The SH3 does not currently require + * barriers, but we must provide the flags to MI code. + */ +#define bus_space_barrier(t, h, o, l, f) \ + ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f))) + +#define BUS_SPACE_BARRIER_READ 0x01 +#define BUS_SPACE_BARRIER_WRITE 0x02 + + +/* + * Bus read (single) operations. + */ +#define bus_space_read_1(t, h, o) __bs_rs(1,uint8_t,(t),(h),(o)) +#define bus_space_read_2(t, h, o) __bs_rs(2,uint16_t,(t),(h),(o)) +#define bus_space_read_4(t, h, o) __bs_rs(4,uint32_t,(t),(h),(o)) +#define bus_space_read_8(t, h, o) __bs_rs(8,uint64_t,(t),(h),(o)) +#define bus_space_read_stream_1(t, h, o) __bs_rss(1,uint8_t,(t),(h),(o)) +#define bus_space_read_stream_2(t, h, o) __bs_rss(2,uint16_t,(t),(h),(o)) +#define bus_space_read_stream_4(t, h, o) __bs_rss(4,uint32_t,(t),(h),(o)) +#define bus_space_read_stream_8(t, h, o) __bs_rss(8,uint64_t,(t),(h),(o)) + + +/* + * Bus read multiple operations. + */ +#define bus_space_read_multi_1(t, h, o, a, c) \ + __bs_nonsingle(rm,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_2(t, h, o, a, c) \ + __bs_nonsingle(rm,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_4(t, h, o, a, c) \ + __bs_nonsingle(rm,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_8(t, h, o, a, c) \ + __bs_nonsingle(rm,8,uint64_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle(rms,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle(rms,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle(rms,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle(rms,8,uint64_t,(t),(h),(o),(a),(c)) + + +/* + * Bus read region operations. + */ +#define bus_space_read_region_1(t, h, o, a, c) \ + __bs_nonsingle(rr,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_2(t, h, o, a, c) \ + __bs_nonsingle(rr,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_4(t, h, o, a, c) \ + __bs_nonsingle(rr,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_8(t, h, o, a, c) \ + __bs_nonsingle(rr,8,uint64_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle(rrs,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle(rrs,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle(rrs,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle(rrs,8,uint64_t,(t),(h),(o),(a),(c)) + + +/* + * Bus write (single) operations. + */ +#define bus_space_write_1(t, h, o, v) __bs_ws(1,uint8_t,(t),(h),(o),(v)) +#define bus_space_write_2(t, h, o, v) __bs_ws(2,uint16_t,(t),(h),(o),(v)) +#define bus_space_write_4(t, h, o, v) __bs_ws(4,uint32_t,(t),(h),(o),(v)) +#define bus_space_write_8(t, h, o, v) __bs_ws(8,uint64_t,(t),(h),(o),(v)) +#define bus_space_write_stream_1(t, h, o, v) \ + __bs_wss(1,uint8_t,(t),(h),(o),(v)) +#define bus_space_write_stream_2(t, h, o, v) \ + __bs_wss(2,uint16_t,(t),(h),(o),(v)) +#define bus_space_write_stream_4(t, h, o, v) \ + __bs_wss(4,uint32_t,(t),(h),(o),(v)) +#define bus_space_write_stream_8(t, h, o, v) \ + __bs_wss(8,uint64_t,(t),(h),(o),(v)) + + +/* + * Bus write multiple operations. + */ +#define bus_space_write_multi_1(t, h, o, a, c) \ + __bs_nonsingle(wm,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_2(t, h, o, a, c) \ + __bs_nonsingle(wm,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_4(t, h, o, a, c) \ + __bs_nonsingle(wm,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_8(t, h, o, a, c) \ + __bs_nonsingle(wm,8,uint64_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle(wms,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle(wms,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle(wms,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle(wms,8,uint64_t,(t),(h),(o),(a),(c)) + + +/* + * Bus write region operations. + */ +#define bus_space_write_region_1(t, h, o, a, c) \ + __bs_nonsingle(wr,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_2(t, h, o, a, c) \ + __bs_nonsingle(wr,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_4(t, h, o, a, c) \ + __bs_nonsingle(wr,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_8(t, h, o, a, c) \ + __bs_nonsingle(wr,8,uint64_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle(wrs,1,uint8_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle(wrs,2,uint16_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle(wrs,4,uint32_t,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle(wrs,8,uint64_t,(t),(h),(o),(a),(c)) + + +/* + * Set multiple operations. + */ +#define bus_space_set_multi_1(t, h, o, v, c) \ + __bs_set(sm,1,uint8_t,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_2(t, h, o, v, c) \ + __bs_set(sm,2,uint16_t,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_4(t, h, o, v, c) \ + __bs_set(sm,4,uint32_t,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_8(t, h, o, v, c) \ + __bs_set(sm,8,uint64_t,(t),(h),(o),(v),(c)) + + +/* + * Set region operations. + */ +#define bus_space_set_region_1(t, h, o, v, c) \ + __bs_set(sr,1,uint8_t,(t),(h),(o),(v),(c)) +#define bus_space_set_region_2(t, h, o, v, c) \ + __bs_set(sr,2,uint16_t,(t),(h),(o),(v),(c)) +#define bus_space_set_region_4(t, h, o, v, c) \ + __bs_set(sr,4,uint32_t,(t),(h),(o),(v),(c)) +#define bus_space_set_region_8(t, h, o, v, c) \ + __bs_set(sr,8,uint64_t,(t),(h),(o),(v),(c)) + + +/* + * Copy region operations. + */ +#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ + __bs_copy(1, uint8_t, (t), (h1), (o1), (h2), (o2), (c)) +#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ + __bs_copy(2, uint16_t, (t), (h1), (o1), (h2), (o2), (c)) +#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ + __bs_copy(4, uint32_t, (t), (h1), (o1), (h2), (o2), (c)) +#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ + __bs_copy(8, uint64_t, (t), (h1), (o1), (h2), (o2), (c)) + +/* + * Bus stream operations--defined in terms of non-stream counterparts + */ +#define __BUS_SPACE_HAS_STREAM_METHODS + +#endif /* _KERNEL */ + +/* + * Flags used in various bus DMA methods. + */ +#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ +#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ +#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ +#define BUS_DMA_COHERENT 0x004 /* map memory to not require sync */ +#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ +#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ +#define BUS_DMA_BUS2 0x020 +#define BUS_DMA_BUS3 0x040 +#define BUS_DMA_BUS4 0x080 +#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ +#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ +#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ + +/* Forwards needed by prototypes below. */ +struct mbuf; +struct uio; + +/* + * Operations performed by bus_dmamap_sync(). + */ +#define BUS_DMASYNC_PREREAD 0x01 +#define BUS_DMASYNC_POSTREAD 0x02 +#define BUS_DMASYNC_PREWRITE 0x04 +#define BUS_DMASYNC_POSTWRITE 0x08 + +typedef struct _bus_dma_tag *bus_dma_tag_t; +typedef struct _bus_dmamap *bus_dmamap_t; + +#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) + +/* + * bus_dma_segment_t + * + * Describes a single contiguous DMA transaction. Values + * are suitable for programming into DMA registers. + */ +struct _bus_dma_segment { + bus_addr_t ds_addr; /* DMA address */ + bus_size_t ds_len; /* length of transfer */ + + /* private section */ + bus_addr_t _ds_vaddr; /* virtual address */ +}; +typedef struct _bus_dma_segment bus_dma_segment_t; + +/* + * bus_dma_tag_t + * + * A machine-dependent opaque type describing the implementation of + * DMA for a given bus. + */ + +struct _bus_dma_tag { + void *_cookie; /* cookie used in the guts */ + + /* + * DMA mapping methods. + */ + int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, + bus_size_t, bus_size_t, int, bus_dmamap_t *); + void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); + int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, + bus_size_t, struct proc *, int); + int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, + struct mbuf *, int); + int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, + struct uio *, int); + int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, + bus_dma_segment_t *, int, bus_size_t, int); + void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); + void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, + bus_addr_t, bus_size_t, int); + + /* + * DMA memory utility functions. + */ + int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, + bus_size_t, bus_dma_segment_t *, int, int *, int); + void (*_dmamem_free)(bus_dma_tag_t, + bus_dma_segment_t *, int); + int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, + int, size_t, void **, int); + void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); + paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, + int, off_t, int, int); +}; + +#define bus_dmamap_create(t, s, n, m, b, f, p) \ + (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) +#define bus_dmamap_destroy(t, p) \ + (*(t)->_dmamap_destroy)((t), (p)) +#define bus_dmamap_load(t, m, b, s, p, f) \ + (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) +#define bus_dmamap_load_mbuf(t, m, b, f) \ + (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) +#define bus_dmamap_load_uio(t, m, u, f) \ + (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) +#define bus_dmamap_load_raw(t, m, sg, n, s, f) \ + (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) +#define bus_dmamap_unload(t, p) \ + (*(t)->_dmamap_unload)((t), (p)) +#define bus_dmamap_sync(t, m, o, l, op) \ + (void)((t)->_dmamap_sync ? \ + (*(t)->_dmamap_sync)((t), (m), (o), (l), (op)) : (void)0) + +#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ + (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) +#define bus_dmamem_free(t, sg, n) \ + (*(t)->_dmamem_free)((t), (sg), (n)) +#define bus_dmamem_map(t, sg, n, s, k, f) \ + (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) +#define bus_dmamem_unmap(t, k, s) \ + (*(t)->_dmamem_unmap)((t), (k), (s)) +#define bus_dmamem_mmap(t, sg, n, o, p, f) \ + (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) + +#define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP +#define bus_dmatag_destroy(t) + +/* + * bus_dmamap_t + * + * Describes a DMA mapping. + */ +struct _bus_dmamap { + /* + * PRIVATE MEMBERS: not for use my machine-independent code. + */ + bus_size_t _dm_size; /* largest DMA transfer mappable */ + int _dm_segcnt; /* number of segs this map can map */ + bus_size_t _dm_maxsegsz; /* largest possible segment */ + bus_size_t _dm_boundary; /* don't cross this */ + int _dm_flags; /* misc. flags */ + + void *_dm_cookie; /* cookie for bus-specific functions */ + + /* + * PUBLIC MEMBERS: these are used by machine-independent code. + */ + bus_size_t dm_mapsize; /* size of the mapping */ + int dm_nsegs; /* # valid segments in mapping */ + bus_dma_segment_t dm_segs[1]; /* segments; variable length */ +}; + +#if defined(_EVBSH3_BUS_DMA_PRIVATE) +int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, + bus_size_t, int, bus_dmamap_t *); +void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); +int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, + struct proc *, int); +int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *,int); +int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int); +int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, bus_dma_segment_t *, + int, bus_size_t, int); +void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); +void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, + bus_size_t, int); -#include +int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size, + bus_size_t alignment, bus_size_t boundary, bus_dma_segment_t *segs, + int nsegs, int *rsegs, int flags); +void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, + int nsegs); +int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs, int nsegs, + size_t size, void **kvap, int flags); +void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, size_t size); +paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs, + int nsegs, off_t off, int prot, int flags); +#endif /* _EVBSH3_BUS_DMA_PRIVATE */ -#endif /* _EVBSH3_BUS_H_ */ +#endif /* _EVBSH3_BUS_H_ */ diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/include/pci_machdep.h src-sh4a/sys/arch/evbsh3/include/pci_machdep.h --- src-sh4a.orig/sys/arch/evbsh3/include/pci_machdep.h 1970-01-01 09:00:00.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/include/pci_machdep.h 2010-01-14 15:05:00.000000000 +0900 @@ -0,0 +1,100 @@ +/* $NetBSD$ */ + +/* + * Copyright (c) 2010 NONAKA Kimihiro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _EVBSH3_PCI_MACHDEP_H +#define _EVBSH3_PCI_MACHDEP_H + +/* + * Machine-specific definitions for PCI autoconfiguration. + */ +#define __HAVE_PCI_CONF_HOOK + +/* + * Types provided to machine-independent PCI code + */ +typedef void *pci_chipset_tag_t; +typedef int pcitag_t; +typedef int pci_intr_handle_t; + +#include + +/* + * Forward declarations. + */ +struct pci_attach_args; + +/* + * Functions provided to machine-independent PCI code. + */ +void evbsh3_pci_attach_hook(struct device *, struct device *, + struct pcibus_attach_args *); +int evbsh3_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); +const char *evbsh3_pci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); +const struct evcnt *evbsh3_pci_intr_evcnt(pci_chipset_tag_t,pci_intr_handle_t); +void *evbsh3_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, int, + int (*)(void *), void *); +void evbsh3_pci_intr_disestablish(pci_chipset_tag_t, void *); +void evbsh3_pci_conf_interrupt(void *v, int bus, int dev, int pin, + int swiz, int *iline); +int evbsh3_pci_conf_hook(void *, int, int, int, pcireg_t); + +#define pci_bus_maxdevs(v, busno) \ + shpcic_bus_maxdevs(v, busno) +#define pci_make_tag(v, bus, dev, func) \ + shpcic_make_tag(v, bus, dev, func) +#define pci_decompose_tag(v, tag, bp, dp, fp) \ + shpcic_decompose_tag(v, tag, bp, dp, fp) +#define pci_conf_read(v, tag, reg) \ + shpcic_conf_read(v, tag, reg) +#define pci_conf_write(v, tag, reg, data) \ + shpcic_conf_write(v, tag, reg, data) + +#define pci_attach_hook(pa, self, pba) \ + evbsh3_pci_attach_hook(pa, self, pba) +#define pci_intr_map(pa, ihp) \ + evbsh3_pci_intr_map(pa, ihp) +#define pci_intr_string(v, ih) \ + evbsh3_pci_intr_string(v, ih) +#define pci_intr_evcnt(v, ih) \ + evbsh3_pci_intr_evcnt(v, ih) +#define pci_intr_establish(v, ih, level, ih_fun, ih_arg) \ + evbsh3_pci_intr_establish(v, ih, level, ih_fun, ih_arg) +#define pci_intr_disestablish(v, cookie) \ + evbsh3_pci_intr_disestablish(v, cookie) +#define pci_conf_interrupt(v, bus, dev, pin, swiz, iline) \ + evbsh3_pci_conf_interrupt(v, bus, dev, pin, swiz, iline) +#define pci_conf_hook(v, bus, dev, func, id) \ + evbsh3_pci_conf_hook(v, bus, dev, func, id) + +#ifdef _KERNEL +/* + * ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED + * BY PORTABLE CODE. + */ +#endif + +#endif /* _EVBSH3_PCI_MACHDEP_H */ diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/renesas7785lcr/machdep.c src-sh4a/sys/arch/evbsh3/renesas7785lcr/machdep.c --- src-sh4a.orig/sys/arch/evbsh3/renesas7785lcr/machdep.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/renesas7785lcr/machdep.c 2010-04-06 14:51:38.000000000 +0900 @@ -159,10 +159,11 @@ void intc_intr(int ssr, int spc, int ssp) { - static uint8_t heartbeat; +//XXXNONAKA static uint8_t heartbeat; uint32_t intevc = *INTEVT; struct intr_table *handler = intr_table + (intevc >> 3); + handler->evcnt.ev_count++; // printf ("%d<=\n", handler->level); if (intevc == 0x580) { //TMU0 TUNI0 struct clockframe cf; @@ -177,7 +178,7 @@ // printf("device done\n"); } - led(heartbeat ^= 1); +//XXXNONAKA led(heartbeat ^= 1); } // Renesas evaluation board R0P7785LC0011RL specific functions. diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/evbsh3/renesas7785lcr/shpcic_machdep.c src-sh4a/sys/arch/evbsh3/renesas7785lcr/shpcic_machdep.c --- src-sh4a.orig/sys/arch/evbsh3/renesas7785lcr/shpcic_machdep.c 1970-01-01 09:00:00.000000000 +0900 +++ src-sh4a/sys/arch/evbsh3/renesas7785lcr/shpcic_machdep.c 2010-03-23 20:24:43.000000000 +0900 @@ -0,0 +1,290 @@ +/* $NetBSD$ */ + +/* + * Copyright (c) 2010 NONAKA Kimihiro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Machine-specific functions for PCI autoconfiguration. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +static int shpcic_match(device_t, cfdata_t, void *); +static void shpcic_attach(device_t, device_t, void *); + +CFATTACH_DECL_NEW(shpcic, 0, + shpcic_match, shpcic_attach, NULL, NULL); + +static int +shpcic_match(device_t parent, cfdata_t cf, void *aux) +{ + + return shpcic_match_common(parent, cf, aux); +} + +static void +shpcic_attach(device_t parent, device_t self, void *aux) +{ + + shpcic_attach_common(parent, self, aux, SH7780PCIC_FLAGS_NO_RESET); +} + +bus_space_tag_t +shpcic_get_bus_io_tag(void) +{ + extern struct _bus_space renesas7785lcr_pci_bus_io; + + return &renesas7785lcr_pci_bus_io; +} + +bus_space_tag_t +shpcic_get_bus_mem_tag(void) +{ + extern struct _bus_space renesas7785lcr_pci_bus_mem; + + return &renesas7785lcr_pci_bus_mem; +} + +bus_dma_tag_t +shpcic_get_bus_dma_tag(void) +{ + extern struct _bus_dma_tag evbsh3_bus_dma; + + return &evbsh3_bus_dma; +} + +void +evbsh3_pci_attach_hook(struct device *parent, struct device *self, + struct pcibus_attach_args *pba) +{ + + /* Nothing to do */ +} + +int +evbsh3_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) +{ + int pin = pa->pa_intrpin; + int line = pa->pa_intrline; + + if (pin == 0) { + /* No IRQ used. */ + goto bad; + } + + if (pin > 4) { + printf("pci_intr_map: bad interrupt pin %d\n", pin); + goto bad; + } + + if (line == 255) { + printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); + goto bad; + } + + *ihp = line; + return 0; + +bad: + *ihp = -1; + return 1; +} + +const char * +evbsh3_pci_intr_string(void *v, pci_intr_handle_t ih) +{ + static char irqstr[8]; /* 4 + 2 + NULL + sanity */ + + sprintf(irqstr, "irq %d", ih); + + return (irqstr); +} + +const struct evcnt * +evbsh3_pci_intr_evcnt(void *v, pci_intr_handle_t ih) +{ + + /* XXX for now, no evcnt parent reported */ + return (NULL); +} + +void * +evbsh3_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, + int (*ih_fun)(void *), void *ih_arg) +{ + int evtcode; + + evtcode = 0xa20 + (ih << 5); + return intc_intr_establish(evtcode, IST_LEVEL, level, ih_fun, ih_arg); +} + +void +evbsh3_pci_intr_disestablish(void *v, void *cookie) +{ + + intc_intr_disestablish(cookie); +} + +void +evbsh3_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, + int *iline) +{ + static const int irq[4] = { 0, 1, 2, 3 }; + + *iline = -1; + if ((dev >= 0 && dev <= 3) && (pin >= 1 && pin <= 4)) { + *iline = irq[(dev + pin - 1) & 3]; + } +} + +int +evbsh3_pci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id) +{ + + return PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; +} + +/* + * shpcic bus space + */ +struct _bus_space renesas7785lcr_pci_bus_io = +{ + .bs_cookie = NULL, + + .bs_map = shpcic_iomem_map, + .bs_unmap = shpcic_iomem_unmap, + .bs_subregion = shpcic_iomem_subregion, + + .bs_alloc = shpcic_iomem_alloc, + .bs_free = shpcic_iomem_free, + + .bs_mmap = shpcic_iomem_mmap, + + .bs_r_1 = shpcic_io_read_1, + .bs_r_2 = shpcic_io_read_2, + .bs_r_4 = shpcic_io_read_4, + + .bs_rm_1 = shpcic_io_read_multi_1, + .bs_rm_2 = shpcic_io_read_multi_2, + .bs_rm_4 = shpcic_io_read_multi_4, + + .bs_rr_1 = shpcic_io_read_region_1, + .bs_rr_2 = shpcic_io_read_region_2, + .bs_rr_4 = shpcic_io_read_region_4, + + .bs_w_1 = shpcic_io_write_1, + .bs_w_2 = shpcic_io_write_2, + .bs_w_4 = shpcic_io_write_4, + + .bs_wm_1 = shpcic_io_write_multi_1, + .bs_wm_2 = shpcic_io_write_multi_2, + .bs_wm_4 = shpcic_io_write_multi_4, + + .bs_wr_1 = shpcic_io_write_region_1, + .bs_wr_2 = shpcic_io_write_region_2, + .bs_wr_4 = shpcic_io_write_region_4, + + .bs_sm_1 = shpcic_io_set_multi_1, + .bs_sm_2 = shpcic_io_set_multi_2, + .bs_sm_4 = shpcic_io_set_multi_4, + + .bs_sr_1 = shpcic_io_set_region_1, + .bs_sr_2 = shpcic_io_set_region_2, + .bs_sr_4 = shpcic_io_set_region_4, + + .bs_c_1 = shpcic_io_copy_region_1, + .bs_c_2 = shpcic_io_copy_region_2, + .bs_c_4 = shpcic_io_copy_region_4, +}; + +struct _bus_space renesas7785lcr_pci_bus_mem = +{ + .bs_cookie = NULL, + + .bs_map = shpcic_iomem_map, + .bs_unmap = shpcic_iomem_unmap, + .bs_subregion = shpcic_iomem_subregion, + + .bs_alloc = shpcic_iomem_alloc, + .bs_free = shpcic_iomem_free, + + .bs_mmap = shpcic_iomem_mmap, + + .bs_r_1 = shpcic_mem_read_1, + .bs_r_2 = shpcic_mem_read_2, + .bs_r_4 = shpcic_mem_read_4, + + .bs_rm_1 = shpcic_mem_read_multi_1, + .bs_rm_2 = shpcic_mem_read_multi_2, + .bs_rm_4 = shpcic_mem_read_multi_4, + + .bs_rr_1 = shpcic_mem_read_region_1, + .bs_rr_2 = shpcic_mem_read_region_2, + .bs_rr_4 = shpcic_mem_read_region_4, + + .bs_w_1 = shpcic_mem_write_1, + .bs_w_2 = shpcic_mem_write_2, + .bs_w_4 = shpcic_mem_write_4, + + .bs_wm_1 = shpcic_mem_write_multi_1, + .bs_wm_2 = shpcic_mem_write_multi_2, + .bs_wm_4 = shpcic_mem_write_multi_4, + + .bs_wr_1 = shpcic_mem_write_region_1, + .bs_wr_2 = shpcic_mem_write_region_2, + .bs_wr_4 = shpcic_mem_write_region_4, + + .bs_sm_1 = shpcic_mem_set_multi_1, + .bs_sm_2 = shpcic_mem_set_multi_2, + .bs_sm_4 = shpcic_mem_set_multi_4, + + .bs_sr_1 = shpcic_mem_set_region_1, + .bs_sr_2 = shpcic_mem_set_region_2, + .bs_sr_4 = shpcic_mem_set_region_4, + + .bs_c_1 = shpcic_mem_copy_region_1, + .bs_c_2 = shpcic_mem_copy_region_2, + .bs_c_4 = shpcic_mem_copy_region_4, +}; diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/7785/clock.c src-sh4a/sys/arch/sh3/7785/clock.c --- src-sh4a.orig/sys/arch/sh3/7785/clock.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/7785/clock.c 2010-04-06 18:08:50.000000000 +0900 @@ -29,7 +29,7 @@ __KERNEL_RCSID(0, "$NetBSD$"); #include - +#include #include #include @@ -39,7 +39,7 @@ #include #ifndef HZ -#define HZ 64 +#define HZ 64 #endif static vaddr_t timer_base[] = { T0_BASE, T1_BASE, T2_BASE, @@ -87,17 +87,17 @@ int -sh_clock_get_pclock() +sh_clock_get_pclock(void) { - return cpg_pck (); + return cpg_pck(); } int -sh_clock_get_cpuclock() +sh_clock_get_cpuclock(void) { - return cpg_ick (); + return cpg_ick(); } u_int @@ -114,10 +114,14 @@ void -cpu_initclocks() +cpu_initclocks(void) { static struct timecounter __tc; // don't allocate stack. + /* Set global variables. */ + hz = HZ; + tick = 1000000 / hz; + // Hard clock. timer_start(TIMER0, 1000000 / HZ, COUNTER_USEC, COUNTER_RESET, TRUE); //XXX timer_start(TIMER0, 1000, COUNTER_MSEC, COUNTER_RESET, TRUE); @@ -214,7 +218,7 @@ } bool -tmu_start (int channel, enum timer_cmd cmd) +tmu_start(int channel, enum timer_cmd cmd) { volatile uint8_t *start_reg; uint8_t bit; @@ -231,13 +235,13 @@ { case TIMER_START: *start_reg |= bit; - return TRUE; + return true; case TIMER_STOP: *start_reg &= ~bit; - return TRUE; + return true; case TIMER_BUSY: return *start_reg & bit; } - return FALSE; + return false; } diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/7785/cpg.c src-sh4a/sys/arch/sh3/7785/cpg.c --- src-sh4a.orig/sys/arch/sh3/7785/cpg.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/7785/cpg.c 2010-04-06 18:07:51.000000000 +0900 @@ -27,23 +27,26 @@ #include "opt_sh4a_input_clock.h" #include -__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.20 2008/04/28 20:23:35 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD$"); #include #include -static int cpg_freq[] = { 0, 18 * 8, 9 * 8, 6 * 8, 9 * 4, - 3 * 8, 9 * 2, 2 * 8, 3 * 4, 9, 8, 3 * 2 }; +static const int cpg_freq[] = { 0, 18 * 8, 9 * 8, 6 * 8, 9 * 4, + 3 * 8, 9 * 2, 2 * 8, 3 * 4, 9, 8, 3 * 2 }; #define CPG_FREQ_SCALE (SH4A_CPUMODE >= 16 ? 8/*mode 16-19*/ : 4/*mode 0-3*/) void -cpg_dump() +cpg_dump(void) { - const char *clk [] = { "P", "DU", "GDTA", "DDR", "B", "SH", "U", "I" }; - int div[] ={ 0, 2, 4, 6, 8, 12, 16, 18, - 24, 32, 36, 48, -1, -1, -1, -1 }; + static const char *clk [] = { + "P", "DU", "GDTA", "DDR", "B", "SH", "U", "I" + }; + static const int div[] = { + 0, 2, 4, 6, 8, 12, 16, 18, 24, 32, 36, 48, -1, -1, -1, -1 + }; uint32_t r = *FRQMR1; int i; @@ -60,23 +63,23 @@ } uint32_t -cpg_pck() +cpg_pck(void) { uint32_t r = *FRQMR1; - uint32_t hz = SH4A_INPUT_CLOCK / + uint32_t h = SH4A_INPUT_CLOCK / CPG_FREQ_SCALE * cpg_freq[(r >> PFC_SHIFT) & 0xf]; - return hz; + return h; } uint32_t -cpg_ick() +cpg_ick(void) { uint32_t r = *FRQMR1; - uint32_t hz = SH4A_INPUT_CLOCK / + uint32_t h = SH4A_INPUT_CLOCK / CPG_FREQ_SCALE * cpg_freq[(r >> IFC_SHIFT) & 0xf]; - return hz; + return h; } diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/7785/intc.h src-sh4a/sys/arch/sh3/7785/intc.h --- src-sh4a.orig/sys/arch/sh3/7785/intc.h 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/7785/intc.h 2010-03-30 22:56:37.000000000 +0900 @@ -28,18 +28,51 @@ #ifndef _INTC_H_ #define _INTC_H_ +#include + +#define ICR0 ((volatile uint32_t *)0xffd00000) +#define INTPRI ((volatile uint32_t *)0xffd00010) +#define ICR1 ((volatile uint32_t *)0xffd0001c) +#define INTREQ ((volatile uint32_t *)0xffd00024) +#define INTMSK0 ((volatile uint32_t *)0xffd00044) +#define INTMSK1 ((volatile uint32_t *)0xffd00048) +#define INTMSKCLR0 ((volatile uint32_t *)0xffd00064) +#define INTMSKCLR1 ((volatile uint32_t *)0xffd00068) +#define INTMSK2 ((volatile uint32_t *)0xffd40080) +#define INTMSKCLR2 ((volatile uint32_t *)0xffd40084) +#define NMIFCR ((volatile uint32_t *)0xffd000c0) + +#define USERIMASK ((volatile uint32_t *)0xffd30000) + #define INT2MSKR ((volatile uint32_t *)0xffd40038) #define INT2MSKCR ((volatile uint32_t *)0xffd4003c) + #define INT2PRI0 ((volatile uint32_t *)0xffd40000) #define INT2PRI1 ((volatile uint32_t *)0xffd40004) #define INT2PRI2 ((volatile uint32_t *)0xffd40008) +#define INT2PRI3 ((volatile uint32_t *)0xffd4000c) +#define INT2PRI4 ((volatile uint32_t *)0xffd40010) +#define INT2PRI5 ((volatile uint32_t *)0xffd40014) +#define INT2PRI6 ((volatile uint32_t *)0xffd40018) +#define INT2PRI7 ((volatile uint32_t *)0xffd4001c) +#define INT2PRI8 ((volatile uint32_t *)0xffd40020) +#define INT2PRI9 ((volatile uint32_t *)0xffd40024) + +#define INT2A0 ((volatile uint32_t *)0xffd40030) +#define INT2A1 ((volatile uint32_t *)0xffd40034) +#define INT2B0 ((volatile uint32_t *)0xffd40040) +#define INT2B1 ((volatile uint32_t *)0xffd40044) +#define INT2B2 ((volatile uint32_t *)0xffd40048) +#define INT2B3 ((volatile uint32_t *)0xffd4004c) +#define INT2B4 ((volatile uint32_t *)0xffd40050) +#define INT2B5 ((volatile uint32_t *)0xffd40054) +#define INT2B6 ((volatile uint32_t *)0xffd40058) +#define INT2B7 ((volatile uint32_t *)0xffd4005c) -#define INT2B0 ((volatile uint32_t *)0xffd40040) -#define INT2A0 ((volatile uint32_t *)0xffd40030) -#define INT2A1 ((volatile uint32_t *)0xffd40034) +#define INT2GPIC ((volatile uint32_t *)0xffd40090) -#define EXPEVT ((volatile uint32_t *)0xff000024) -#define INTEVT ((volatile uint32_t *)0xff000028) +#define EXPEVT ((volatile uint32_t *)0xff000024) +#define INTEVT ((volatile uint32_t *)0xff000028) __BEGIN_DECLS typedef int (intr_handler_t)(void *); @@ -47,6 +80,7 @@ intr_handler_t *func; void *arg; int level; + struct evcnt evcnt; }; extern struct intr_table intr_table[]; __END_DECLS diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/7785/interrupt.c src-sh4a/sys/arch/sh3/7785/interrupt.c --- src-sh4a.orig/sys/arch/sh3/7785/interrupt.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/7785/interrupt.c 2010-04-04 14:09:32.000000000 +0900 @@ -35,16 +35,39 @@ #include #include -intr_handler_t null_intr; +static void _intc_intr_enable(int, int); +#if 0 +static void _intc_intr_disable(int); +#endif +static intr_handler_t null_intr; struct intr_table intr_table[512]; // INTEVT: 0x1c0-0xfe0 -> 56-508 +static const char *intr_names[] = { + "0x000", "0x020", "0x040", "0x060", "0x080", "0x0a0", "0x0c0", "0x0e0", + "0x100", "0x120", "0x140", "0x160", "0x180", "0x1a0", "0x1c0", "0x1e0", + "0x200", "0x220", "0x240", "0x260", "0x280", "0x2a0", "0x2c0", "0x2e0", + "0x300", "0x320", "0x340", "0x360", "0x380", "0x3a0", "0x3c0", "0x3e0", + "0x400", "0x420", "0x440", "0x460", "0x480", "0x4a0", "0x4c0", "0x4e0", + "0x500", "0x520", "0x540", "0x560", "TUNI0", "TUNI1", "TUNI2", "0x5e0", + "0x600", "0x620", "0x640", "0x660", "0x680", "0x6a0", "0x6c0", "0x6e0", + "0x700", "0x720", "0x740", "0x760", "ERI1", "RXI1", "BRI1", "TXI1", + "0x800", "0x820", "0x840", "0x860", "0x880", "0x8a0", "0x8c0", "0x8e0", + "0x900", "0x920", "0x940", "0x960", "0x980", "0x9a0", "0x9c0", "0x9e0", + "PCIC0", "PCIC1", "PCIC2", "PCIC3", "PCIC4", "0xaa0", "0xac0", "0xae0", + "0xb00", "0xb20", "0xb40", "0xb60", "0xb80", "0xba0", "0xbc0", "0xbe0", + "0xc00", "0xc20", "0xc40", "0xc60", "0xc80", "0xca0", "0xcc0", "0xce0", + "0xd00", "0xd20", "0xd40", "0xd60", "0xd80", "0xda0", "0xdc0", "0xde0", + "0xe00", "0xe20", "0xe40", "0xe60", "0xe80", "0xea0", "0xec0", "0xee0", + "0xf00", "0xf20", "0xf40", "0xf60", "0xf80", "0xfa0", "0xfc0", "0xfe0", +}; + void intc_init(void) { size_t i; - for (i = 0; i < sizeof intr_table / sizeof (intr_table[0]); i++) + for (i = 0; i < __arraycount(intr_table); i++) intr_table[i].func = null_intr; } @@ -57,7 +80,9 @@ p->func = ih_func; p->arg = ih_arg; p->level = level; - intc_intr_enable(intevt); + evcnt_attach_dynamic(&p->evcnt, EVCNT_TYPE_INTR, NULL, "intc", + intr_names[intevt >> 5]); + _intc_intr_enable(intevt, level); return p; } @@ -67,49 +92,84 @@ { struct intr_table *p = (struct intr_table *)arg; + evcnt_detach(&p->evcnt); p->func = null_intr; p->arg = NULL; } -void -intc_intr_enable(int intevt) +static void +_intc_intr_enable(int intevt, int level) { + int pri = (level == IPL_HIGH) ? 0x1f : (level << 1); switch (intevt) { case 0x580: // TMU0 TUNI0 *INT2MSKCR = 1; // unmask TMU0-2 // Set priority. - *INT2PRI0 |= 0x1f000000; + *INT2PRI0 |= pri << 24; break; case 0x5a0: // TMU1 TUNI1 *INT2MSKCR = 1; // unmask TMU0-2 - *INT2PRI0 |= 0x001f0000; + *INT2PRI0 |= pri << 16; break; case 0x5c0: // TMU2 TUNI2 *INT2MSKCR = 1; // unmask TMU0-2 - *INT2PRI0 |= 0x00001f00; + *INT2PRI0 |= pri << 8; break; - case 0x780: + case 0x780: // SCIF-ch1 ERI1 *INT2MSKCR = 1 << 3; - *INT2PRI2 |= 0x000f0000; + *INT2PRI2 |= pri << 16; break; - case 0x7a0: + case 0x7a0: // SCIF-ch1 RXI1 *INT2MSKCR = 1 << 3; - *INT2PRI2 |= 0x000f0000; + *INT2PRI2 |= pri << 16; break; - case 0x7c0: + case 0x7c0: // SCIF-ch1 BRI1 *INT2MSKCR = 1 << 3; - *INT2PRI2 |= 0x000f0000; + *INT2PRI2 |= pri << 16; break; - case 0x7e0: + case 0x7e0: // SCIF-ch1 TXI1 *INT2MSKCR = 1 << 3; - *INT2PRI2 |= 0x000f0000; + *INT2PRI2 |= pri << 16; + break; + case 0xa00: // PCISERR: PCIC(0) + *INT2MSKCR = 1 << 14; + *INT2PRI5 |= pri << 8; + break; + case 0xa20: // PCIINTA: PCIC(1) + *INT2MSKCR = 1 << 15; + *INT2PRI5 |= pri; + break; + case 0xa40: // PCIINTB: PCIC(2) + *INT2MSKCR = 1 << 16; + *INT2PRI6 |= pri << 24; + break; + case 0xa60: // PCIINTC: PCIC(3) + *INT2MSKCR = 1 << 17; + *INT2PRI6 |= pri << 16; + break; + case 0xa80: // PCIINTD: PCIC(4) + *INT2MSKCR = 1 << 18; + *INT2PRI6 |= pri << 8; + break; + case 0xaa0: // PCIERR: PCIC(5) + *INT2MSKCR = 1 << 19; + *INT2PRI6 |= pri; + break; + case 0xac0: // PCIPWD[1-3]: PCIC(5) + *INT2MSKCR = 1 << 19; + *INT2PRI6 |= pri; + break; + case 0xae0: // PCIPWD0: PCIC(5) + *INT2MSKCR = 1 << 19; + *INT2PRI6 |= pri; break; } } -void -intc_intr_disable(int intevt) +#if 0 +static void +_intc_intr_disable(int intevt) { switch (intevt) { @@ -122,8 +182,33 @@ case 0x5c0: // TMU2 TUNI2 *INT2PRI0 &= ~0x00001f00; break; + case 0xa00: // PCISERR: PCIC(0) + *INT2PRI5 &= ~0x00001f00; + break; + case 0xa20: // PCIINTA: PCIC(1) + *INT2PRI5 &= ~0x0000001f; + break; + case 0xa40: // PCIINTB: PCIC(2) + *INT2PRI6 &= ~0x1f000000; + break; + case 0xa60: // PCIINTC: PCIC(3) + *INT2PRI6 &= ~0x001f0000; + break; + case 0xa80: // PCIINTD: PCIC(4) + *INT2PRI6 &= ~0x00001f00; + break; + case 0xaa0: // PCIERR: PCIC(5) + *INT2PRI6 &= ~0x0000001f; + break; + case 0xac0: // PCIPWD[1-3]: PCIC(5) + *INT2PRI6 &= ~0x0000001f; + break; + case 0xae0: // PCIPWD0: PCIC(5) + *INT2PRI6 &= ~0x0000001f; + break; } } +#endif bool cpu_intr_p(void) @@ -132,12 +217,12 @@ return curcpu()->ci_idepth >= 0; } -int -null_intr (void *ctx) +static int +null_intr(void *ctx) { - uint32_t intevt = *INTEVT; + uint32_t intevt = *INTEVT; - printf("%x %x\n", intevt, intevt >> 3); - panic("interrupt handler missing"); - return 0; + printf("%x %x\n", intevt, intevt >> 3); + panic("interrupt handler missing"); + return 0; } diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/conf/files.shpcic src-sh4a/sys/arch/sh3/conf/files.shpcic --- src-sh4a.orig/sys/arch/sh3/conf/files.shpcic 2005-12-11 21:18:58.000000000 +0900 +++ src-sh4a/sys/arch/sh3/conf/files.shpcic 2010-01-14 14:55:25.000000000 +0900 @@ -1,9 +1,9 @@ # $NetBSD: files.shpcic,v 1.2 2005/12/11 12:18:58 christos Exp $ # -# SH7751{,R} integrated PCI controller +# SH7751{,R}, SH778[05] integrated PCI controller # device shpcic: pcibus attach shpcic at mainbus - file arch/sh3/dev/shpcic.c sh4 & shpcic +file arch/sh3/dev/sh7780pcic.c sh4a & shpcic diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/dev/sh7780pcic.c src-sh4a/sys/arch/sh3/dev/sh7780pcic.c --- src-sh4a.orig/sys/arch/sh3/dev/sh7780pcic.c 1970-01-01 09:00:00.000000000 +0900 +++ src-sh4a/sys/arch/sh3/dev/sh7780pcic.c 2010-04-06 15:33:08.000000000 +0900 @@ -0,0 +1,1211 @@ +/* $NetBSD$ */ + +/* + * Copyright (c) 2010 NONAKA Kimihiro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include "opt_pci.h" + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#if defined(DEBUG) && !defined(SHPCIC_DEBUG) +#define SHPCIC_DEBUG 0 +#endif +#if defined(SHPCIC_DEBUG) +int shpcic_debug = SHPCIC_DEBUG + 0; +#define DPRINTF(arg) if (shpcic_debug) printf arg +#else +#define DPRINTF(arg) +#endif + +#define PCI_MODE1_ENABLE 0x80000000UL + +#define PCI_MEM_ADDR32 0xc0000000UL +#define PCI_MEM_SIZE32 512 + +extern struct cfdriver shpcic_cd; + +int +shpcic_match_common(device_t parent, cfdata_t cf, void *aux) +{ + struct mainbus_attach_args *ma = aux; + pcireg_t id; + + if (strcmp(ma->ma_name, shpcic_cd.cd_name) != 0) + return 0; + + switch (cpu_product) { + case CPU_PRODUCT_7780: + case CPU_PRODUCT_7785: + break; + + default: + return 0; + } + + _reg_write_4(SH7780_PCIECR, PCIECR_ENBL); + + id = _reg_read_4(SH7780_PCIVID); + + switch (PCI_VENDOR(id)) { + case PCI_VENDOR_RENESAS: + break; + + default: + goto fail; + } + + switch (PCI_PRODUCT(id)) { + case PCI_PRODUCT_RENESAS_SH7780: + case PCI_PRODUCT_RENESAS_SH7785: + break; + + default: + goto fail; + } + + _reg_write_4(SH7780_PCIECR, 0); + return 1; + +fail: + _reg_write_4(SH7780_PCIECR, 0); + return 0; +} + +void +shpcic_attach_common(device_t parent, device_t self, void *aux, uint flags) +{ + struct pcibus_attach_args pba; +#ifdef PCI_NETBSD_CONFIGURE + struct extent *ioext, *memext; + paddr_t memstart, memsize; +#endif + + aprint_naive("\n"); + aprint_normal("\n"); + + _reg_write_4(SH7780_PCIECR, PCIECR_ENBL); + + if ((flags & SH7780PCIC_FLAGS_NO_RESET) == 0) { + /* Initialize PCIC */ + _reg_write_4(SH7780_PCICR, PCICR_BASE | PCICR_RSTCTL); + delay(100 * 1000); + _reg_write_4(SH7780_PCICR, PCICR_BASE); + } + + /* Enable I/O, memory, bus-master */ + _reg_write_4(SH7780_PCICMD, PCI_COMMAND_IO_ENABLE + | PCI_COMMAND_MEM_ENABLE + | PCI_COMMAND_MASTER_ENABLE + | PCI_COMMAND_PARITY_ENABLE); + + /* Class: Host-Bridge */ + _reg_write_4(SH7780_PCIRID, + PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 0x00)); + +#define PCILSR(s) (((((s) << 20) - 1) & 0xfff00000) | 1) +#if defined(SH4A_EXT_ADDR32) + /* set PCI local address 0 */ + _reg_write_4(SH7780_PCILSR0, PCILSR(512)); + _reg_write_4(SH7780_PCILAR0, 0x40000000); + _reg_write_4(SH7780_PCIMBAR0, 0x40000000); + + /* set PCI local address 1 */ + _reg_write_4(SH7780_PCILSR1, 0); + _reg_write_4(SH7780_PCILAR1, 0); + _reg_write_4(SH7780_PCIMBAR1, 0); +#else + /* set PCI local address 0 */ + _reg_write_4(SH7780_PCILSR0, PCILSR(128)); + _reg_write_4(SH7780_PCILAR0, 0xa8000000); + _reg_write_4(SH7780_PCIMBAR0, 0xa8000000); + + /* set PCI local address 1 */ + _reg_write_4(SH7780_PCILSR1, PCILSR(128)); + _reg_write_4(SH7780_PCILAR1, 0xa8000000); + _reg_write_4(SH7780_PCIMBAR1, 0x88000000); +#endif +#undef PCILSR + + _reg_write_4(SH7780_PCIMBR0, SH7780_PCIC_MEM); + _reg_write_4(SH7780_PCIMBMR0, (SH7780_PCIC_MEM_SIZE - 1) & 0xfc0000); + + _reg_write_4(SH7780_PCIMBR1, 0x10000000); + _reg_write_4(SH7780_PCIMBMR1, ((64 << 20) - 1) & 0x3fc0000); + + _reg_write_4(SH7780_PCIMBR2, PCI_MEM_ADDR32); + _reg_write_4(SH7780_PCIMBMR2, ((PCI_MEM_SIZE32 << 20) - 1) & 0x1ffc0000); + + /* set PCI I/O, memory base address */ + _reg_write_4(SH7780_PCIIOBR, SH7780_PCIC_IO); + _reg_write_4(SH7780_PCIIOBMR, (SH7780_PCIC_IO_SIZE - 1) & 0x1c0000); + + /* disable snoop */ + _reg_write_4(SH7780_PCICSCR0, 0); + _reg_write_4(SH7780_PCICSCR1, 0); + _reg_write_4(SH7780_PCICSAR0, 0); + _reg_write_4(SH7780_PCICSAR1, 0); + +// sh7780pcic_fixup_hook(); + + /* Initialize done. */ + _reg_write_4(SH7780_PCICR, PCICR_BASE + | PCICR_PFCS + | PCICR_FTO + | PCICR_PFE + | PCICR_BMABT + | PCICR_CFINIT); + +#ifdef PCI_NETBSD_CONFIGURE + /* configure PCI bus */ + ioext = extent_create("pciio", + SH7780_PCIC_IO, SH7780_PCIC_IO + SH7780_PCIC_IO_SIZE - 1, + M_DEVBUF, NULL, 0, EX_NOWAIT); +#if defined(SH4A_EXT_ADDR32) + memstart = PCI_MEM_ADDR32; + memsize = PCI_MEM_SIZE32 * 1024 * 1024; +#else + memstart = SH7780_PCIC_MEM; + memsize = SH7780_PCIC_MEM_SIZE; +#endif + memext = extent_create("pcimem", memstart, memstart + memsize - 1, + M_DEVBUF, NULL, 0, EX_NOWAIT); + + pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size); + + extent_destroy(ioext); + extent_destroy(memext); +#endif + + /* PCI bus */ + memset(&pba, 0, sizeof(pba)); + pba.pba_iot = shpcic_get_bus_io_tag(); + pba.pba_memt = shpcic_get_bus_mem_tag(); + pba.pba_dmat = shpcic_get_bus_dma_tag(); + pba.pba_dmat64 = NULL; + pba.pba_pc = NULL; + pba.pba_bus = 0; + pba.pba_bridgetag = NULL; + pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; + config_found(self, &pba, NULL); +} + +int +shpcic_bus_maxdevs(void *v, int busno) +{ + + /* + * Bus number is irrelevant. Configuration Mechanism 1 is in + * use, can have devices 0-32 (i.e. the `normal' range). + */ + return 32; +} + +pcitag_t +shpcic_make_tag(void *v, int bus, int device, int function) +{ + pcitag_t tag; + + if (bus >= 256 || device >= 32 || function >= 8) + panic("pci_make_tag: bad request"); + + tag = PCI_MODE1_ENABLE | + (bus << 16) | (device << 11) | (function << 8); + + return tag; +} + +void +shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) +{ + + if (bp != NULL) + *bp = (tag >> 16) & 0xff; + if (dp != NULL) + *dp = (tag >> 11) & 0x1f; + if (fp != NULL) + *fp = (tag >> 8) & 0x7; +} + +pcireg_t +shpcic_conf_read(void *v, pcitag_t tag, int reg) +{ + pcireg_t data; + int s; + + s = splhigh(); + _reg_write_4(SH7780_PCIPAR, tag | reg); + data = _reg_read_4(SH7780_PCIPDR); + splx(s); + + return data; +} + +void +shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) +{ + int s; + + s = splhigh(); + _reg_write_4(SH7780_PCIPAR, tag | reg); + _reg_write_4(SH7780_PCIPDR, data); + splx(s); +} + +void * +shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg) +{ + + return intc_intr_establish(evtcode, IST_LEVEL, IPL_BIO, ih_func, ih_arg); /*XXXNONAKA*/ +} + +void +shpcic_intr_disestablish(void *ih) +{ + + intc_intr_disestablish(ih); +} + +/* + * shpcic bus space + */ +int +shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, + int flags, bus_space_handle_t *bshp) +{ + + *bshp = (bus_space_handle_t)bpa; + + return (0); +} + +void +shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) +{ + + /* Nothing to do */ +} + +int +shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) +{ + + *nbshp = bsh + offset; + + return (0); +} + +int +shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, + bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, + bus_addr_t *bpap, bus_space_handle_t *bshp) +{ + + *bshp = *bpap = rstart; + + return (0); +} + +void +shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size) +{ + + /* Nothing to do */ +} + +paddr_t +shpcic_iomem_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) +{ + + return (paddr_t)-1; +} + +/* + * shpcic bus space io/mem read/write + */ +/* read */ +static inline uint8_t __shpcic_io_read_1(bus_space_handle_t bsh, + bus_size_t offset); +static inline uint16_t __shpcic_io_read_2(bus_space_handle_t bsh, + bus_size_t offset); +static inline uint32_t __shpcic_io_read_4(bus_space_handle_t bsh, + bus_size_t offset); +static inline uint8_t __shpcic_mem_read_1(bus_space_handle_t bsh, + bus_size_t offset); +static inline uint16_t __shpcic_mem_read_2(bus_space_handle_t bsh, + bus_size_t offset); +static inline uint32_t __shpcic_mem_read_4(bus_space_handle_t bsh, + bus_size_t offset); + +static inline uint8_t +__shpcic_io_read_1(bus_space_handle_t bsh, bus_size_t offset) +{ + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_IO_MASK; + + return *(volatile uint8_t *)(SH7780_PCIC_IO + adr); +} + +static inline uint16_t +__shpcic_io_read_2(bus_space_handle_t bsh, bus_size_t offset) +{ + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_IO_MASK; + + return *(volatile uint16_t *)(SH7780_PCIC_IO + adr); +} + +static inline uint32_t +__shpcic_io_read_4(bus_space_handle_t bsh, bus_size_t offset) +{ + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_IO_MASK; + + return *(volatile uint32_t *)(SH7780_PCIC_IO + adr); +} + +static inline uint8_t +__shpcic_mem_read_1(bus_space_handle_t bsh, bus_size_t offset) +{ +#if defined(SH4A_EXT_ADDR32) + u_long adr = (u_long)(bsh + offset); + + return *(volatile uint8_t *)(PCI_MEM_ADDR32 + adr); +#else + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_MEM_MASK; + + return *(volatile uint8_t *)(SH7780_PCIC_MEM + adr); +#endif +} + +static inline uint16_t +__shpcic_mem_read_2(bus_space_handle_t bsh, bus_size_t offset) +{ +#if defined(SH4A_EXT_ADDR32) + u_long adr = (u_long)(bsh + offset); + + return *(volatile uint16_t *)(PCI_MEM_ADDR32 + adr); +#else + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_MEM_MASK; + + return *(volatile uint16_t *)(SH7780_PCIC_MEM + adr); +#endif +} + +static inline uint32_t +__shpcic_mem_read_4(bus_space_handle_t bsh, bus_size_t offset) +{ +#if defined(SH4A_EXT_ADDR32) + u_long adr = (u_long)(bsh + offset); + + return *(volatile uint32_t *)(PCI_MEM_ADDR32 + adr); +#else + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_MEM_MASK; + + return *(volatile uint32_t *)(SH7780_PCIC_MEM + adr); +#endif +} + +/* + * read single + */ +uint8_t +shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset) +{ + uint8_t value; + + value = __shpcic_io_read_1(bsh, offset); + + return value; +} + +uint16_t +shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset) +{ + uint16_t value; + + value = __shpcic_io_read_2(bsh, offset); + + return value; +} + +uint32_t +shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset) +{ + uint32_t value; + + value = __shpcic_io_read_4(bsh, offset); + + return value; +} + +uint8_t +shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset) +{ + uint8_t value; + + value = __shpcic_mem_read_1(bsh, offset); + + return value; +} + +uint16_t +shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset) +{ + uint16_t value; + + value = __shpcic_mem_read_2(bsh, offset); + + return value; +} + +uint32_t +shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset) +{ + uint32_t value; + + value = __shpcic_mem_read_4(bsh, offset); + + return value; +} + +/* + * read multi + */ +void +shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_io_read_1(bsh, offset); + } +} + +void +shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_io_read_2(bsh, offset); + } +} + +void +shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_io_read_4(bsh, offset); + } +} + +void +shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_mem_read_1(bsh, offset); + } +} + +void +shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_mem_read_2(bsh, offset); + } +} + +void +shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_mem_read_4(bsh, offset); + } +} + +/* + * + * read region + */ +void +shpcic_io_read_region_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_io_read_1(bsh, offset); + offset += 1; + } +} + +void +shpcic_io_read_region_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_io_read_2(bsh, offset); + offset += 2; + } +} + +void +shpcic_io_read_region_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_io_read_4(bsh, offset); + offset += 4; + } +} + +void +shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_mem_read_1(bsh, offset); + offset += 1; + } +} + +void +shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_mem_read_2(bsh, offset); + offset += 2; + } +} + +void +shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t *addr, bus_size_t count) +{ + + while (count--) { + *addr++ = __shpcic_mem_read_4(bsh, offset); + offset += 4; + } +} + +/* write */ +static inline void __shpcic_io_write_1(bus_space_handle_t bsh, + bus_size_t offset, uint8_t value); +static inline void __shpcic_io_write_2(bus_space_handle_t bsh, + bus_size_t offset, uint16_t value); +static inline void __shpcic_io_write_4(bus_space_handle_t bsh, + bus_size_t offset, uint32_t value); +static inline void __shpcic_mem_write_1(bus_space_handle_t bsh, + bus_size_t offset, uint8_t value); +static inline void __shpcic_mem_write_2(bus_space_handle_t bsh, + bus_size_t offset, uint16_t value); +static inline void __shpcic_mem_write_4(bus_space_handle_t bsh, + bus_size_t offset, uint32_t value); + +static inline void +__shpcic_io_write_1(bus_space_handle_t bsh, bus_size_t offset, + uint8_t value) +{ + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_IO_MASK; + + *(volatile uint8_t *)(SH7780_PCIC_IO + adr) = value; +} + +static inline void +__shpcic_io_write_2(bus_space_handle_t bsh, bus_size_t offset, + uint16_t value) +{ + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_IO_MASK; + + *(volatile uint16_t *)(SH7780_PCIC_IO + adr) = value; +} + +static inline void +__shpcic_io_write_4(bus_space_handle_t bsh, bus_size_t offset, + uint32_t value) +{ + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_IO_MASK; + + *(volatile uint32_t *)(SH7780_PCIC_IO + adr) = value; +} + +static inline void +__shpcic_mem_write_1(bus_space_handle_t bsh, bus_size_t offset, + uint8_t value) +{ +#if defined(SH4A_EXT_ADDR32) + u_long adr = (u_long)(bsh + offset); + + *(volatile uint8_t *)(PCI_MEM_ADDR32 + adr) = value; +#else + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_MEM_MASK; + + *(volatile uint8_t *)(SH7780_PCIC_MEM + adr) = value; +#endif +} + +static inline void +__shpcic_mem_write_2(bus_space_handle_t bsh, bus_size_t offset, + uint16_t value) +{ +#if defined(SH4A_EXT_ADDR32) + u_long adr = (u_long)(bsh + offset); + + *(volatile uint16_t *)(PCI_MEM_ADDR32 + adr) = value; +#else + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_MEM_MASK; + + *(volatile uint16_t *)(SH7780_PCIC_MEM + adr) = value; +#endif +} + +static inline void +__shpcic_mem_write_4(bus_space_handle_t bsh, bus_size_t offset, + uint32_t value) +{ +#if defined(SH4A_EXT_ADDR32) + u_long adr = (u_long)(bsh + offset); + + *(volatile uint32_t *)(PCI_MEM_ADDR32 + adr) = value; +#else + u_long adr = (u_long)(bsh + offset) & SH7780_PCIC_MEM_MASK; + + *(volatile uint32_t *)(SH7780_PCIC_MEM + adr) = value; +#endif +} + +/* + * write single + */ +void +shpcic_io_write_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t value) +{ + + __shpcic_io_write_1(bsh, offset, value); +} + +void +shpcic_io_write_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t value) +{ + + __shpcic_io_write_2(bsh, offset, value); +} + +void +shpcic_io_write_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t value) +{ + + __shpcic_io_write_4(bsh, offset, value); +} + +void +shpcic_mem_write_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t value) +{ + + __shpcic_mem_write_1(bsh, offset, value); +} + +void +shpcic_mem_write_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t value) +{ + + __shpcic_mem_write_2(bsh, offset, value); +} + +void +shpcic_mem_write_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t value) +{ + + __shpcic_mem_write_4(bsh, offset, value); +} + +/* + * write multi + */ +void +shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint8_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_1(bsh, offset, *addr++); + } +} + +void +shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint16_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_2(bsh, offset, *addr++); + } +} + +void +shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint32_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_4(bsh, offset, *addr++); + } +} + +void +shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint8_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_1(bsh, offset, *addr++); + } +} + +void +shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint16_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_2(bsh, offset, *addr++); + } +} + +void +shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint32_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_4(bsh, offset, *addr++); + } +} + +/* + * write region + */ +void +shpcic_io_write_region_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint8_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_1(bsh, offset, *addr++); + offset += 1; + } +} + +void +shpcic_io_write_region_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint16_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_2(bsh, offset, *addr++); + offset += 2; + } +} + +void +shpcic_io_write_region_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint32_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_4(bsh, offset, *addr++); + offset += 4; + } +} + +void +shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint8_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_1(bsh, offset, *addr++); + offset += 1; + } +} + +void +shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint16_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_2(bsh, offset, *addr++); + offset += 2; + } +} + +void +shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, const uint32_t *addr, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_4(bsh, offset, *addr++); + offset += 4; + } +} + +/* + * set multi + */ +void +shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_1(bsh, offset, value); + } +} + +void +shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_2(bsh, offset, value); + } +} + +void +shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_4(bsh, offset, value); + } +} + +void +shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_1(bsh, offset, value); + } +} + +void +shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_2(bsh, offset, value); + } +} + +void +shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_4(bsh, offset, value); + } +} + +/* + * set region + */ +void +shpcic_io_set_region_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_1(bsh, offset, value); + offset += 1; + } +} + +void +shpcic_io_set_region_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_2(bsh, offset, value); + offset += 2; + } +} + +void +shpcic_io_set_region_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_io_write_4(bsh, offset, value); + offset += 4; + } +} + +void +shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint8_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_1(bsh, offset, value); + offset += 1; + } +} + +void +shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint16_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_2(bsh, offset, value); + offset += 2; + } +} + +void +shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh, + bus_size_t offset, uint32_t value, bus_size_t count) +{ + + while (count--) { + __shpcic_mem_write_4(bsh, offset, value); + offset += 4; + } +} + +/* + * copy region + */ +void +shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count) +{ + u_long addr1 = bsh1 + off1; + u_long addr2 = bsh2 + off2; + uint8_t value; + + if (addr1 >= addr2) { /* src after dest: copy forward */ + while (count--) { + value = __shpcic_io_read_1(bsh1, off1); + __shpcic_io_write_1(bsh2, off2, value); + off1 += 1; + off2 += 1; + } + } else { /* dest after src: copy backwards */ + off1 += (count - 1) * 1; + off2 += (count - 1) * 1; + while (count--) { + value = __shpcic_io_read_1(bsh1, off1); + __shpcic_io_write_1(bsh2, off2, value); + off1 -= 1; + off2 -= 1; + } + } +} + +void +shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count) +{ + u_long addr1 = bsh1 + off1; + u_long addr2 = bsh2 + off2; + uint16_t value; + + if (addr1 >= addr2) { /* src after dest: copy forward */ + while (count--) { + value = __shpcic_io_read_2(bsh1, off1); + __shpcic_io_write_2(bsh2, off2, value); + off1 += 2; + off2 += 2; + } + } else { /* dest after src: copy backwards */ + off1 += (count - 1) * 2; + off2 += (count - 1) * 2; + while (count--) { + value = __shpcic_io_read_2(bsh1, off1); + __shpcic_io_write_2(bsh2, off2, value); + off1 -= 2; + off2 -= 2; + } + } +} + +void +shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count) +{ + u_long addr1 = bsh1 + off1; + u_long addr2 = bsh2 + off2; + uint32_t value; + + if (addr1 >= addr2) { /* src after dest: copy forward */ + while (count--) { + value = __shpcic_io_read_4(bsh1, off1); + __shpcic_io_write_4(bsh2, off2, value); + off1 += 4; + off2 += 4; + } + } else { /* dest after src: copy backwards */ + off1 += (count - 1) * 4; + off2 += (count - 1) * 4; + while (count--) { + value = __shpcic_io_read_4(bsh1, off1); + __shpcic_io_write_4(bsh2, off2, value); + off1 -= 4; + off2 -= 4; + } + } +} + +void +shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count) +{ + u_long addr1 = bsh1 + off1; + u_long addr2 = bsh2 + off2; + uint8_t value; + + if (addr1 >= addr2) { /* src after dest: copy forward */ + while (count--) { + value = __shpcic_mem_read_1(bsh1, off1); + __shpcic_mem_write_1(bsh2, off2, value); + off1 += 1; + off2 += 1; + } + } else { /* dest after src: copy backwards */ + off1 += (count - 1) * 1; + off2 += (count - 1) * 1; + while (count--) { + value = __shpcic_mem_read_1(bsh1, off1); + __shpcic_mem_write_1(bsh2, off2, value); + off1 -= 1; + off2 -= 1; + } + } +} + +void +shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count) +{ + u_long addr1 = bsh1 + off1; + u_long addr2 = bsh2 + off2; + uint16_t value; + + if (addr1 >= addr2) { /* src after dest: copy forward */ + while (count--) { + value = __shpcic_mem_read_2(bsh1, off1); + __shpcic_mem_write_2(bsh2, off2, value); + off1 += 2; + off2 += 2; + } + } else { /* dest after src: copy backwards */ + off1 += (count - 1) * 2; + off2 += (count - 1) * 2; + while (count--) { + value = __shpcic_mem_read_2(bsh1, off1); + __shpcic_mem_write_2(bsh2, off2, value); + off1 -= 2; + off2 -= 2; + } + } +} + +void +shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count) +{ + u_long addr1 = bsh1 + off1; + u_long addr2 = bsh2 + off2; + uint32_t value; + + if (addr1 >= addr2) { /* src after dest: copy forward */ + while (count--) { + value = __shpcic_mem_read_4(bsh1, off1); + __shpcic_mem_write_4(bsh2, off2, value); + off1 += 4; + off2 += 4; + } + } else { /* dest after src: copy backwards */ + off1 += (count - 1) * 4; + off2 += (count - 1) * 4; + while (count--) { + value = __shpcic_mem_read_4(bsh1, off1); + __shpcic_mem_write_4(bsh2, off2, value); + off1 -= 4; + off2 -= 4; + } + } +} diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/dev/shpcicvar.h src-sh4a/sys/arch/sh3/dev/shpcicvar.h --- src-sh4a.orig/sys/arch/sh3/dev/shpcicvar.h 2009-08-02 09:15:28.000000000 +0900 +++ src-sh4a/sys/arch/sh3/dev/shpcicvar.h 2010-01-15 11:32:40.000000000 +0900 @@ -29,8 +29,13 @@ #ifndef _SH3_SHPCICVAR_H_ #define _SH3_SHPCICVAR_H_ +#include #include +int shpcic_match_common(device_t, cfdata_t, void *); +void shpcic_attach_common(device_t, device_t, void *, uint); +#define SH7780PCIC_FLAGS_NO_RESET (1 << 0) + bus_space_tag_t shpcic_get_bus_io_tag(void); bus_space_tag_t shpcic_get_bus_mem_tag(void); bus_dma_tag_t shpcic_get_bus_dma_tag(void); diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/include/cache_sh4a.h src-sh4a/sys/arch/sh3/include/cache_sh4a.h --- src-sh4a.orig/sys/arch/sh3/include/cache_sh4a.h 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/include/cache_sh4a.h 2010-03-29 21:03:07.000000000 +0900 @@ -153,9 +153,7 @@ void sh4a_dcache_inv_range (vaddr_t, vsize_t); void sh4a_dcache_wb_range (vaddr_t, vsize_t); void sh4a_dcache_wbinv_range_index (vaddr_t, vsize_t); -#ifdef DEBUG void sh4a_dcache_array_dump (vaddr_t, vsize_t); -#endif __END_DECLS diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/include/mmu_sh4a.h src-sh4a/sys/arch/sh3/include/mmu_sh4a.h --- src-sh4a.orig/sys/arch/sh3/include/mmu_sh4a.h 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/include/mmu_sh4a.h 2010-03-29 21:06:28.000000000 +0900 @@ -367,11 +367,9 @@ bool sh4a_pmb_align_check (uint32_t, uint32_t); #endif -#ifdef DEBUG void sh4a_mmu_itlb_dump (void); void sh4a_mmu_utlb_dump (void); void sh4a_mmu_dump (void); -#endif void sh4a_mmu_start (void); void sh4a_tlb_clear_all (void); diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/include/pcicreg.h src-sh4a/sys/arch/sh3/include/pcicreg.h --- src-sh4a.orig/sys/arch/sh3/include/pcicreg.h 2005-12-11 21:18:58.000000000 +0900 +++ src-sh4a/sys/arch/sh3/include/pcicreg.h 2010-01-12 17:05:31.000000000 +0900 @@ -1,7 +1,7 @@ /* $NetBSD: pcicreg.h,v 1.2 2005/12/11 12:18:58 christos Exp $ */ /*- - * Copyright (c) 2005 NONAKA Kimihiro + * Copyright (c) 2005, 2010 NONAKA Kimihiro * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ #include /* - * PCI Controller + * SH7751/SH7751R PCI Controller */ #define SH4_PCIC 0xfe200000 @@ -142,4 +142,91 @@ #define PCIIOBR_MASK 0xffc00000 + +/* + * SH7780/SH7785 PCI Controller + */ + +#define SH7780_PCIC_IO 0xfe200000 +#define SH7780_PCIC_IO_SIZE 0x00200000 +#define SH7780_PCIC_IO_MASK (SH7780_PCIC_IO_SIZE-1) +#define SH7780_PCIC_MEM 0xfd000000 +#define SH7780_PCIC_MEM_SIZE 0x01000000 +#define SH7780_PCIC_MEM_MASK (SH7780_PCIC_MEM_SIZE-1) + +#define SH7780_PCIECR 0xfe000008 + +#define SH7780_PCIVID 0xfe040000 +#define SH7780_PCIDID 0xfe040002 +#define SH7780_PCICMD 0xfe040004 +#define SH7780_PCISTATUS 0xfe040006 +#define SH7780_PCIRID 0xfe040008 +#define SH7780_PCIPIF 0xfe040009 +#define SH7780_PCISUB 0xfe04000a +#define SH7780_PCIBCC 0xfe04000b +#define SH7780_PCICLS 0xfe04000c +#define SH7780_PCILTM 0xfe04000d +#define SH7780_PCIHDR 0xfe04000e +#define SH7780_PCIBIST 0xfe04000f +#define SH7780_PCIIBAR 0xfe040010 +#define SH7780_PCIMBAR0 0xfe040014 +#define SH7780_PCIMBAR1 0xfe040018 +#define SH7780_PCISVID 0xfe04002c +#define SH7780_PCISID 0xfe04002e +#define SH7780_PCICP 0xfe040034 +#define SH7780_PCIINTLINE 0xfe04003c +#define SH7780_PCIINTPIN 0xfe04003d +#define SH7780_PCIMINGNT 0xfe04003e +#define SH7780_PCIMAXLAT 0xfe04003f +#define SH7780_PCICID 0xfe040040 +#define SH7780_PCINIP 0xfe040041 +#define SH7780_PCIPMC 0xfe040042 +#define SH7780_PCIPMCSR 0xfe040044 +#define SH7780_PCIPMCSRBSE 0xfe040046 +#define SH7780_PCIPCDD 0xfe040047 + +#define SH7780_PCICR 0xfe040100 +#define SH7780_PCILSR0 0xfe040104 +#define SH7780_PCILSR1 0xfe040108 +#define SH7780_PCILAR0 0xfe04010c +#define SH7780_PCILAR1 0xfe040110 +#define SH7780_PCIIR 0xfe040114 +#define SH7780_PCIIMR 0xfe040118 +#define SH7780_PCIAIR 0xfe04011c +#define SH7780_PCICIR 0xfe040120 +#define SH7780_PCIAINT 0xfe040130 +#define SH7780_PCIAINTM 0xfe040134 +#define SH7780_PCIBMIR 0xfe040138 +#define SH7780_PCIPAR 0xfe0401c0 +#define SH7780_PCIPINT 0xfe0401cc +#define SH7780_PCIPINTM 0xfe0401d0 +#define SH7780_PCIMBR0 0xfe0401e0 +#define SH7780_PCIMBMR0 0xfe0401e4 +#define SH7780_PCIMBR1 0xfe0401e8 +#define SH7780_PCIMBMR1 0xfe0401ec +#define SH7780_PCIMBR2 0xfe0401f0 +#define SH7780_PCIMBMR2 0xfe0401f4 +#define SH7780_PCIIOBR 0xfe0401f8 +#define SH7780_PCIIOBMR 0xfe0401fc +#define SH7780_PCICSCR0 0xfe040210 +#define SH7780_PCICSCR1 0xfe040214 +#define SH7780_PCICSAR0 0xfe040218 +#define SH7780_PCICSAR1 0xfe04021c +#define SH7780_PCIPDR 0xfe040220 + +/* PCIECR */ +#define PCIECR_ENBL (1 << 0) + +/* PCICR */ +/* PCICR_BASE 0xa5000000 */ +#define PCICR_PFCS 0x00000800 +#define PCICR_FTO 0x00000400 +#define PCICR_PFE 0x00000200 +/* PCICR_BYTESWAP 0x00000100 */ +/* PCICR_BMABT 0x00000040 */ +/* PCICR_SERR 0x00000008 */ +/* PCICR_INTA 0x00000004 */ +/* PCICR_RSTCTL 0x00000002 */ +/* PCICR_CFINIT 0x00000001 */ + #endif /* _SH3_PCICREG_H__ */ diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/cache_sh4a.c src-sh4a/sys/arch/sh3/sh3/cache_sh4a.c --- src-sh4a.orig/sys/arch/sh3/sh3/cache_sh4a.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/cache_sh4a.c 2010-04-06 18:55:38.000000000 +0900 @@ -1,3 +1,4 @@ +/* $NetBSD$ */ /*- * Copyright (c) 2009 UCHIYAMA Yasushi. All rights reserved. @@ -43,11 +44,11 @@ #endif void -sh4a_cache_config () +sh4a_cache_config(void) { - sh4a_cache_disable (); - sh4a_cache_enable (TRUE); // write-back -// sh4a_cache_enable (FALSE); // write-thru + sh4a_cache_disable(); + sh4a_cache_enable(TRUE); // write-back +// sh4a_cache_enable(FALSE); // write-thru uint32_t r = *SH4A_CCR; sh_cache_unified = FALSE; @@ -60,7 +61,7 @@ sh_cache_prefer_mask = SH4A_DCACHE_SIZE / SH4A_CACHE_WAY - 1; sh_cache_write_through_p0_u0_p3 = r & CCR_WT; #ifdef SH4A_EXT_ADDR32 - sh_cache_write_through_p1 = sh4a_pmb_region_write_thru (0); + sh_cache_write_through_p1 = sh4a_pmb_region_write_thru(0); #else sh_cache_write_through_p1 = !(r & CCR_CB); #endif @@ -87,7 +88,7 @@ void _cpu_run_P1(void); void -sh4a_cache_enable (bool write_back) +sh4a_cache_enable(bool write_back) { // CCR modifications must only be made by program in the P2(uncached) area. _cpu_run_P2(); @@ -108,19 +109,19 @@ *SH4A_CCR |= CCR_WT; #endif // After CCR has been updated, execute the ICBI instruction for any address. - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); // Return to P1(cacheable) again. _cpu_run_P1(); } void -sh4a_cache_disable () +sh4a_cache_disable(void) { // CCR modifications must only be made by program in the P2(uncached) area. _cpu_run_P2(); // Before invalidate, write-back all. - sh4a_dcache_wbinv_all (); + sh4a_dcache_wbinv_all(); // Reset cache. invalidate all. *SH4A_CCR |= (CCR_ICI | CCR_OCI); @@ -129,13 +130,13 @@ *SH4A_CCR &= ~(CCR_ICE | CCR_OCE); // After CCR has been updated, execute the ICBI instruction for any address. - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); // Return to P1(cacheable) again. _cpu_run_P1(); } void -sh4a_icache_sync_all () +sh4a_icache_sync_all(void) { // printf("%s\n", __FUNCTION__); @@ -145,7 +146,7 @@ uint32_t addr; // D-cache writeback invalidate. - sh4a_dcache_wbinv_all (); // Index ops. + sh4a_dcache_wbinv_all(); // Index ops. // I-cache invalidate for (entry = 0; entry < SH4A_CACHE_ENTRY; entry++) @@ -157,20 +158,20 @@ *(volatile uint32_t *)(addr | (2 << CCIA_WAY_SHIFT)) &= ~CCIA_V; *(volatile uint32_t *)(addr | (3 << CCIA_WAY_SHIFT)) &= ~CCIA_V; } - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); _cpu_run_P1(); } void -sh4a_icache_sync_range (vaddr_t va, vsize_t sz) +sh4a_icache_sync_range(vaddr_t va, vsize_t sz) { // printf("%s\n", __FUNCTION__); // round/truncate with cache line. - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); - sh4a_dcache_wbinv_range (va, sz); + sh4a_dcache_wbinv_range(va, sz); while (va < eva) { @@ -181,21 +182,21 @@ } void -sh4a_icache_sync_range_index (vaddr_t va, vsize_t sz) +sh4a_icache_sync_range_index(vaddr_t va, vsize_t sz) { // printf("%s\n", __FUNCTION__); _cpu_run_P2(); - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); if (sz > SH4A_ICACHE_SIZE) { - sh4a_icache_sync_all (); + sh4a_icache_sync_all(); return; } - sh4a_dcache_wbinv_range_index (va, sz); + sh4a_dcache_wbinv_range_index(va, sz); while (va < eva) { @@ -206,12 +207,12 @@ *(volatile uint32_t *)(addr | (3 << CCIA_WAY_SHIFT)) &= ~CCIA_V; va += SH4A_CACHE_LINESZ; } - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); _cpu_run_P1(); } void -sh4a_dcache_wbinv_all () +sh4a_dcache_wbinv_all(void) { // printf("%s\n", __FUNCTION__); @@ -230,23 +231,23 @@ *(volatile uint32_t *)(addr | (2 << CCDA_WAY_SHIFT)) &= ~(CCDA_U | CCDA_V); *(volatile uint32_t *)(addr | (3 << CCDA_WAY_SHIFT)) &= ~(CCDA_U | CCDA_V); } - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); _cpu_run_P1(); } void -sh4a_dcache_wbinv_range (vaddr_t va, vsize_t sz) +sh4a_dcache_wbinv_range(vaddr_t va, vsize_t sz) { // printf("%s\n", __FUNCTION__); if (sz > SH4A_DCACHE_SIZE) { - sh4a_dcache_wbinv_all (); // Index ops. + sh4a_dcache_wbinv_all(); // Index ops. return; } - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); while (va < eva) { @@ -258,10 +259,10 @@ } void -sh4a_dcache_inv_range (vaddr_t va, vsize_t sz) +sh4a_dcache_inv_range(vaddr_t va, vsize_t sz) { - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); while (va < eva) { @@ -277,12 +278,12 @@ } void -sh4a_dcache_wb_range (vaddr_t va, vsize_t sz) +sh4a_dcache_wb_range(vaddr_t va, vsize_t sz) { // printf("%s\n", __FUNCTION__); - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); while (va < eva) { @@ -294,17 +295,17 @@ } void -sh4a_dcache_wbinv_range_index (vaddr_t va, vsize_t sz) +sh4a_dcache_wbinv_range_index(vaddr_t va, vsize_t sz) { // printf("%s\n", __FUNCTION__); _cpu_run_P2(); - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); if (sz > SH4A_DCACHE_SIZE) { - sh4a_dcache_wbinv_all (); // Index ops. + sh4a_dcache_wbinv_all(); // Index ops. return; } @@ -317,7 +318,7 @@ *(volatile uint32_t *)(addr | (3 << CCIA_WAY_SHIFT)) &= ~(CCDA_U | CCDA_V); va += SH4A_CACHE_LINESZ; } - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); _cpu_run_P1(); } @@ -326,11 +327,11 @@ #ifdef DDB #define printf db_printf void -sh4a_dcache_array_dump (vaddr_t va, vsize_t sz) +sh4a_dcache_array_dump(vaddr_t va, vsize_t sz) { _cpu_run_P2(); - vsize_t eva = ROUND_CACHELINE_32 (va + sz); - va = TRUNC_CACHELINE_32 (va); + vsize_t eva = ROUND_CACHELINE_32(va + sz); + va = TRUNC_CACHELINE_32(va); size_t j, k; @@ -362,7 +363,7 @@ va += SH4A_CACHE_LINESZ; } - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); _cpu_run_P1(); } diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/cpu.c src-sh4a/sys/arch/sh3/sh3/cpu.c --- src-sh4a.orig/sys/arch/sh3/sh3/cpu.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/cpu.c 2010-04-06 18:30:06.000000000 +0900 @@ -68,8 +68,8 @@ #define MHZ(x) ((x) / 1000000), (((x) % 1000000) / 1000) aprint_naive("\n"); - aprint_normal(": SH%d%c %d.%02d MHz PCLOCK %d.%02d MHz\n", - CPU_IS_SH3 ? 3 : 4, CPU_IS_SH4A ? 'A' : ' ', + aprint_normal(": SH%d%s %d.%02d MHz PCLOCK %d.%02d MHz\n", + CPU_IS_SH3 ? 3 : 4, CPU_IS_SH4A ? "A" : "", MHZ(sh_clock_get_cpuclock()), MHZ(sh_clock_get_pclock())); #undef MHZ diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/db_interface.c src-sh4a/sys/arch/sh3/sh3/db_interface.c --- src-sh4a.orig/sys/arch/sh3/sh3/db_interface.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/db_interface.c 2010-03-29 21:04:01.000000000 +0900 @@ -422,6 +422,7 @@ } #endif /* SH4 */ #ifdef SH4A + void sh4a_mmu_dump(void); sh4a_mmu_dump(); #endif } diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/exception.c src-sh4a/sys/arch/sh3/sh3/exception.c --- src-sh4a.orig/sys/arch/sh3/sh3/exception.c 2010-03-21 14:05:25.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/exception.c 2010-04-06 23:02:28.000000000 +0900 @@ -286,7 +286,7 @@ int err, track, ftype; const char *panic_msg; - pcb = &l->l_addr->u_pcb; + pcb = lwp_getpcb(l); onfault = pcb->pcb_onfault; #define TLB_ASSERT(assert, msg) \ @@ -371,7 +371,7 @@ } map = &l->l_proc->p_vmspace->vm_map; pmap = map->pmap; -#if 1 +#if 0//XXXNONAKA printf("%s: ASID%d\n", __FUNCTION__,pmap->pm_asid); #endif } @@ -429,19 +429,21 @@ else { ksi.ksi_signo = SIGSEGV; ksi.ksi_code = SEGV_MAPERR; +#ifdef DEBUG void sh4a_mmu_dump (void); sh4a_mmu_dump (); +#endif panic(__FUNCTION__); } goto user_fault; } else { -#if 1 - void sh4a_mmu_dump (void); +#ifdef DEBUG + void sh4a_mmu_dump(void); uint32_t r; __asm volatile ("stc spc, %0" : "=r"(r)); printf ("%x\n", tf->tf_r8); printf("!!!!%s %x %x!!!!\n", __FUNCTION__, va, r); - sh4a_mmu_dump (); + sh4a_mmu_dump(); #endif TLB_ASSERT(onfault, diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/exception_vector.S src-sh4a/sys/arch/sh3/sh3/exception_vector.S --- src-sh4a.orig/sys/arch/sh3/sh3/exception_vector.S 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/exception_vector.S 2010-04-06 20:10:50.000000000 +0900 @@ -314,7 +314,7 @@ * and maximum 512 bytes long (== 0x600 - 0x400). */ NENTRY(sh4_vector_tlbmiss) -#if 0 +#ifndef SH4A_EXT_ADDR32 //XXXNONAKA mov.l .L4_SH4_PTEH, r4 mov.l .L4_VPN_cleanup, r0 mov.l @r4, r5 diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/locore_subr.S src-sh4a/sys/arch/sh3/sh3/locore_subr.S --- src-sh4a.orig/sys/arch/sh3/sh3/locore_subr.S 2010-03-21 13:57:21.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/locore_subr.S 2010-04-06 16:26:22.000000000 +0900 @@ -129,7 +129,7 @@ ldc r2, r6_bank mov r3, r15 -#if !defined(P1_STACK) && (defined(SH4) || defined SH4A) +#if !defined(P1_STACK) && (defined(SH4) || defined(SH4A)) !! wire u-area in TLB MOV (switch_resume, r0) jsr @r0 diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/mmu_sh4a.c src-sh4a/sys/arch/sh3/sh3/mmu_sh4a.c --- src-sh4a.orig/sys/arch/sh3/sh3/mmu_sh4a.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/mmu_sh4a.c 2010-04-06 23:03:46.000000000 +0900 @@ -1,3 +1,4 @@ +/* $NetBSD$ */ /*- * Copyright (c) 2009 UCHIYAMA Yasushi. All rights reserved. @@ -38,11 +39,11 @@ #include // PAGE_SIZE #define STATIC static +void tlb_entry_print(uint32_t, uint32_t, uint32_t, int); #ifdef DEBUG -STATIC void tlb_entry_print (uint32_t, uint32_t, uint32_t, int); +void sh4a_mmu_utlb_check(void); #endif -void sh4a_mmu_utlb_check (void); -paddr_t sh4a_mmu_utlb_lookup_by_va (vaddr_t); +paddr_t sh4a_mmu_utlb_lookup_by_va(vaddr_t); static int mmu_paddr; @@ -50,13 +51,16 @@ #define SPECIAL_WIRED 4 void -sh4a_mmu_start () +sh4a_mmu_start(void) { uint32_t r; - - sh4a_mmu_dump (); - sh4a_tlb_clear_all (); - sh4a_mmu_dump (); +#ifdef DEBUG + sh4a_mmu_dump(); +#endif + sh4a_tlb_clear_all(); +#ifdef DEBUG + sh4a_mmu_dump(); +#endif #ifdef SH4A_EXT_ADDR32 *PASCR = PASCR_SE; mmu_paddr = 32; @@ -86,39 +90,39 @@ *SH4A_MMUCR = r; #ifdef NetBSD - sh4a_mmu_wired_set (UPAGES + SPECIAL_WIRED); + sh4a_mmu_wired_set(UPAGES + SPECIAL_WIRED); #endif - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); } void -sh4a_mmu_information () +sh4a_mmu_information(void) { - printf ("cpu0: %dbit physical address mode. ", mmu_paddr); - printf ("TLB-%s mode.\n", mmu_mode ? "extended" : "compatible"); + printf("cpu0: %dbit physical address mode. ", mmu_paddr); + printf("TLB-%s mode.\n", mmu_mode ? "extended" : "compatible"); #ifdef SH4A_EXT_ADDR32 - sh4a_pmb_dump (); + sh4a_pmb_dump(); #endif } void -sh4a_mmu_asid_set (uint32_t acid) +sh4a_mmu_asid_set(uint32_t acid) { *SH4A_PTEH = acid & PTEH_ASID; } uint32_t -sh4a_mmu_asid_get () +sh4a_mmu_asid_get(void) { return *SH4A_PTEH & PTEH_ASID; } void -sh4a_tlb_counter_set (uint32_t n) +sh4a_tlb_counter_set(uint32_t n) { *SH4A_MMUCR &= ~(MMUCR_URC_MASK << MMUCR_URC_SHIFT); @@ -126,20 +130,20 @@ } uint32_t -sh4a_tlb_counter_get () +sh4a_tlb_counter_get(void) { return (*SH4A_MMUCR >> MMUCR_URC_SHIFT) & MMUCR_URC_MASK; } void -sh4a_mmu_wired_set (int n) +sh4a_mmu_wired_set(int n) { uint32_t limit = (SH4A_UTLB_ENTRY - n) & MMUCR_URB_MASK; // If current counter is wired area, reset. - if (sh4a_tlb_counter_get () >= limit) - sh4a_tlb_counter_set (0); + if (sh4a_tlb_counter_get() >= limit) + sh4a_tlb_counter_set(0); // Set coutner limit. *SH4A_MMUCR &= ~(MMUCR_URB_MASK << MMUCR_URB_SHIFT); *SH4A_MMUCR |= (limit << MMUCR_URB_SHIFT); @@ -148,7 +152,7 @@ } uint32_t -sh4a_mmu_wired_get () +sh4a_mmu_wired_get(void) { // return # of wired entry. if URC == URB, URC is setted 0. uint32_t urb = (*SH4A_MMUCR >> MMUCR_URB_SHIFT) & MMUCR_URB_MASK; @@ -157,7 +161,7 @@ } void -sh4a_tlb_clear_all () +sh4a_tlb_clear_all(void) { uint32_t entry, e; @@ -182,14 +186,14 @@ } void -sh4a_tlb_wired_entry (struct tlb_entry *e) +sh4a_tlb_wired_entry(struct tlb_entry *e) { uint32_t pteh, ptel, ptea; #ifdef DEBUG uint32_t pgsz_table[] = { 0x400, 0x1000, 0x1000, 0x100000, 0x2000, 0x40000, 0x400000, 0x4000000 }; - uint32_t pgsz_mask = pgsz_table[e->size] -1; - assert (!(e->vpn & pgsz_mask) && !(e->ppn & pgsz_mask)); + uint32_t pgsz_mask = pgsz_table[e->size] - 1; + assert(!(e->vpn & pgsz_mask) && !(e->ppn & pgsz_mask)); #endif // Set Physical addr - Virtual addr. ptel = e->ppn & PTEL_PPN; @@ -198,21 +202,21 @@ // Shared page don't bother ASID. if (e->shared) - ptel |= PTEL_SH; + ptel |= PTEL_SH; else pteh |= e->asid; // Setup Protect, Cache, Pagesize. - sh4a_tlb_entry_pagesize (e->size, &ptel, &ptea); - sh4a_tlb_entry_protect (e->protect, &ptel, &ptea); - sh4a_tlb_entry_cache (e->cache, &ptel, &ptea); + sh4a_tlb_entry_pagesize(e->size, &ptel, &ptea); + sh4a_tlb_entry_protect(e->protect, &ptel, &ptea); + sh4a_tlb_entry_cache(e->cache, &ptel, &ptea); // Enable this entry. ptel |= (PTEL_V | PTEL_D); // Prepare new wired entry. - uint32_t n = sh4a_mmu_wired_get () + 1; + uint32_t n = sh4a_mmu_wired_get() + 1; // Set URC for LDTLB - sh4a_tlb_counter_set (SH4A_UTLB_ENTRY - n); + sh4a_tlb_counter_set(SH4A_UTLB_ENTRY - n); *SH4A_PTEH = pteh; *SH4A_PTEL = ptel; #ifdef SH4A_EXT_MMU @@ -220,27 +224,27 @@ #endif __asm volatile ("ldtlb"); // Make this wired entry. - sh4a_mmu_wired_set (n); - CPU_SYNC_RESOURCE (); + sh4a_mmu_wired_set(n); + CPU_SYNC_RESOURCE(); #ifdef DEBUG // Valid bit is maped to both address array and data array, but // tlb_entry_print check address array only. XXX - tlb_entry_print (pteh | UTLB_AA_V, ptel, ptea, 0); + tlb_entry_print(pteh | UTLB_AA_V, ptel, ptea, 0); #endif } // Invalidate TLB entry by address. void -sh4a_tlb_invalidate_addr (int asid, vaddr_t va) +sh4a_tlb_invalidate_addr(int asid, vaddr_t va) { int s = _cpu_intr_suspend(); // Save current ASID - uint32_t oasid = sh4a_mmu_asid_get (); + uint32_t oasid = sh4a_mmu_asid_get(); bool save_asid = asid != oasid; // Set ASID for associative write if (save_asid) - sh4a_mmu_asid_set (asid); + sh4a_mmu_asid_set(asid); // Associative write UTLB. ITLB is also invalidated. // SH4A can access by a program in the P1/P2. no need to change P2. @@ -248,20 +252,20 @@ // Restore ASID if (save_asid) - sh4a_mmu_asid_set (oasid); - _cpu_intr_resume (s); + sh4a_mmu_asid_set(oasid); + _cpu_intr_resume(s); } // Invalidate TLB entry by ASID. void -sh4a_tlb_invalidate_asid (int asid) +sh4a_tlb_invalidate_asid(int asid) { int s = _cpu_intr_suspend(); // don't thread switch here. volatile uint32_t *a; uint32_t entry; // I assume asid is not 0. so wired entry is not matched. - assert (asid != 0); + assert(asid != 0); for (entry = 0; entry < SH4A_UTLB_ENTRY; entry++) { a = (volatile uint32_t *)(SH4A_UTLB_AA | (entry << UTLB_AA_E_SHIFT)); @@ -276,12 +280,12 @@ *a = 0; // Drop valid bit. } - _cpu_intr_resume (s); + _cpu_intr_resume(s); } // Invalidate TLB entry exclude wired entry. void -sh4a_tlb_invalidate_all () +sh4a_tlb_invalidate_all(void) { int s = _cpu_intr_suspend(); volatile uint32_t *a; @@ -299,11 +303,11 @@ *a = 0; } - _cpu_intr_resume (s); + _cpu_intr_resume(s); } void -sh4a_tlb_entry_pagesize (int szidx, uint32_t *ptel __attribute__((unused)), +sh4a_tlb_entry_pagesize(int szidx, uint32_t *ptel __attribute__((unused)), uint32_t *ptea __attribute__((unused))) { #ifdef SH4A_EXT_MMU @@ -318,7 +322,7 @@ } void -sh4a_tlb_entry_protect (int pridx, uint32_t *ptel __attribute__((unused)), +sh4a_tlb_entry_protect(int pridx, uint32_t *ptel __attribute__((unused)), uint32_t *ptea __attribute__((unused))) { #ifdef SH4A_EXT_MMU @@ -338,7 +342,7 @@ } void -sh4a_tlb_entry_cache (int cidx, uint32_t *ptel, +sh4a_tlb_entry_cache(int cidx, uint32_t *ptel, uint32_t *ptea __attribute__((unused))) { uint32_t cache_bits[] = { 0, PTEL_C, PTEL_C | PTEL_WT }; @@ -348,7 +352,7 @@ uint32_t -sh4a_mmu_encode_swbits (enum mmu_page_size sz, // 8types. 3bit +sh4a_mmu_encode_swbits(enum mmu_page_size sz, // 8types. 3bit enum mmu_protect pr, // 4types. 2bit uint32_t opt __attribute__((unused))) { @@ -371,15 +375,15 @@ } wired_map[1024]; int -sh4a_wired_counter_alloc (vaddr_t va) +sh4a_wired_counter_alloc(vaddr_t va) { - int i; - for (i = 0; i < 1024; i++) { + + for (i = 0; i < __arraycount(wired_map); i++) { if (!wired_map[i].inuse) { wired_map[i].inuse = TRUE; wired_map[i].va = va; - printf ("%s wired %d alloc\n", __FUNCTION__, i); + printf("%s wired %d alloc\n", __FUNCTION__, i); return 0; // return SH4A_UTLB_ENTRY - UPAGES - SPECIAL_WIRED + i; } @@ -389,28 +393,28 @@ } void -sh4a_wired_counter_dealloc (vaddr_t va) +sh4a_wired_counter_dealloc(vaddr_t va) { - int i, j; - for (i = j = 0; i < 1024; i++) { + + for (i = j = 0; i < __arraycount(wired_map); i++) { bool wired = wired_map[i].inuse; if (wired) { j++; if (wired_map[i].va == va) { wired_map[i].inuse = FALSE; - printf ("%s wired %d dealloc\n", __FUNCTION__, i); + printf("%s wired %d dealloc\n", __FUNCTION__, i); } } } - printf ("tolal %d wired page\n", j); + printf("tolal %d wired page\n", j); } // Load new TLB entry. void sh4a_tlb_update_wired(int asid, vaddr_t va, uint32_t pte) { -// printf ("%s %d %lx %x\n", __FUNCTION__, asid, va, pte); +// printf("%s %d %lx %x\n", __FUNCTION__, asid, va, pte); int s = _cpu_intr_suspend (); va &= ~PGOFSET; @@ -427,19 +431,19 @@ uint32_t ptel = pte & PG_HW_BITS; // Remove software bits *SH4A_PTEL = ptel; - int cnt = sh4a_tlb_counter_get (); + int cnt = sh4a_tlb_counter_get(); // Set wired entry. - sh4a_tlb_counter_set (sh4a_wired_counter_alloc(va)); + sh4a_tlb_counter_set(sh4a_wired_counter_alloc(va)); __asm volatile ("ldtlb"); - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); // Restore counter. - sh4a_tlb_counter_set (cnt); + sh4a_tlb_counter_set(cnt); // Restore ASID if (save_asid) - sh4a_mmu_asid_set (oasid); -// sh4a_mmu_dump (); - _cpu_intr_resume (s); + sh4a_mmu_asid_set(oasid); +// sh4a_mmu_dump(); + _cpu_intr_resume(s); } // Load new TLB entry. @@ -448,17 +452,17 @@ { // printf ("%s %d %lx %x\n", __FUNCTION__, asid, va, pte); - int s = _cpu_intr_suspend (); + int s = _cpu_intr_suspend(); va &= ~PGOFSET; // Save current ASID - uint32_t oasid = sh4a_mmu_asid_get (); + uint32_t oasid = sh4a_mmu_asid_get(); bool save_asid = asid != oasid; if (save_asid) - sh4a_mmu_asid_set (asid); + sh4a_mmu_asid_set(asid); // Invalidate old entry. - sh4a_tlb_invalidate_addr (asid, va); + sh4a_tlb_invalidate_addr(asid, va); // Load new entry. uint32_t vpn = va & PTEH_VPN; @@ -469,7 +473,7 @@ #error notyet uint32_t ptel, ptea; pte = pte; ptel = 0; ptea=0; - // sh4a_mmu_decode_swbits (pte, &ptel, &ptea); + // sh4a_mmu_decode_swbits(pte, &ptel, &ptea); *SH4A_PTEL = ptel; *SH4A_PTEA = ptea; #else @@ -481,20 +485,22 @@ *SH4A_PTEL = ptel; #endif - int cnt = sh4a_tlb_counter_get () + 1; + int cnt = sh4a_tlb_counter_get() + 1; if (cnt > (60 - SPECIAL_WIRED)) cnt = 0; - sh4a_tlb_counter_set (cnt); + sh4a_tlb_counter_set(cnt); __asm volatile ("ldtlb"); - CPU_SYNC_RESOURCE (); + CPU_SYNC_RESOURCE(); // Restore ASID if (save_asid) - sh4a_mmu_asid_set (oasid); - sh4a_mmu_utlb_check (); -// sh4a_mmu_dump (); - _cpu_intr_resume (s); + sh4a_mmu_asid_set(oasid); +#ifdef DEBUG + sh4a_mmu_utlb_check(); +#endif +// sh4a_mmu_dump(); + _cpu_intr_resume(s); } #include "opt_ddb.h" @@ -502,32 +508,32 @@ #include #define printf db_printf void -sh4a_mmu_dump () +sh4a_mmu_dump(void) { - printf ("MMUCR: %x ", *SH4A_MMUCR); - printf ("PTEH: %x ", *SH4A_PTEH); - printf ("PTEL: %x ", *SH4A_PTEL); - printf ("TTB: %x ", *SH4A_TTB); - printf ("TEA: %x ", *SH4A_TEA); + printf("MMUCR: %x ", *SH4A_MMUCR); + printf("PTEH: %x ", *SH4A_PTEH); + printf("PTEL: %x ", *SH4A_PTEL); + printf("TTB: %x ", *SH4A_TTB); + printf("TEA: %x ", *SH4A_TEA); #ifdef SH4A_EXT_MMU - printf ("PTEA: %x", *SH4A_TEA); + printf("PTEA: %x", *SH4A_TEA); #endif - printf ("\n"); - printf ("wired entry:%d\n", sh4a_mmu_wired_get ()); + printf("\n"); + printf("wired entry:%d\n", sh4a_mmu_wired_get ()); - sh4a_mmu_itlb_dump (); - sh4a_mmu_utlb_dump (); + sh4a_mmu_itlb_dump(); + sh4a_mmu_utlb_dump(); #ifdef SH4A_EXT_ADDR32 - printf ("--------------------PMB--------------------\n"); + printf("--------------------PMB--------------------\n"); uint32_t r = *PASCR; - printf ("paddr %dbit mode.\n", r & PASCR_SE ? 32 : 29); - sh4a_pmb_dump (); + printf("paddr %dbit mode.\n", r & PASCR_SE ? 32 : 29); + sh4a_pmb_dump(); #endif } void -sh4a_mmu_itlb_dump () +sh4a_mmu_itlb_dump(void) { uint32_t entry, e, aa, da1, da2; @@ -542,12 +548,12 @@ #else da2 = 0; #endif - tlb_entry_print (aa, da1, da2, entry); + tlb_entry_print(aa, da1, da2, entry); } } void -sh4a_mmu_utlb_dump () +sh4a_mmu_utlb_dump(void) { uint32_t entry, e, aa, da1, da2; @@ -562,7 +568,7 @@ #else da2 = 0; #endif - tlb_entry_print (aa, da1, da2, entry); + tlb_entry_print(aa, da1, da2, entry); } } @@ -571,7 +577,7 @@ vaddr_t utlb_vaddr[SH4A_UTLB_ENTRY]; paddr_t -sh4a_mmu_utlb_lookup_by_va (vaddr_t va) +sh4a_mmu_utlb_lookup_by_va(vaddr_t va) { uint32_t entry, e, aa, da1; paddr_t pa = 0; @@ -584,7 +590,7 @@ if ((aa & UTLB_AA_VPN) == va) { da1 = *(volatile uint32_t *)(SH4A_UTLB_DA1 | e); pa = da1 & UTLB_DA1_PPN; - tlb_entry_print (aa, da1, 0, entry); + tlb_entry_print(aa, da1, 0, entry); return pa; } } @@ -595,7 +601,7 @@ void -sh4a_mmu_utlb_check () +sh4a_mmu_utlb_check(void) { uint32_t entry, e, aa; @@ -603,7 +609,7 @@ { e = entry << UTLB_AA_E_SHIFT; aa = *(volatile uint32_t *)(SH4A_UTLB_AA | e); - utlb_vaddr[entry] = aa & UTLB_AA_V ? (aa & (UTLB_AA_VPN | UTLB_AA_ASID)) + utlb_vaddr[entry] = aa & UTLB_AA_V ? (aa & (UTLB_AA_VPN | UTLB_AA_ASID)) : 0xffffffff; } @@ -621,7 +627,7 @@ printf("TLB double hit %x\n", a0); sh4a_mmu_utlb_dump(); while (/*CONSTCOND*/1) - ; + continue; } } } @@ -629,7 +635,7 @@ } void -tlb_entry_print (uint32_t aa, uint32_t da1, uint32_t da2, int n) +tlb_entry_print(uint32_t aa, uint32_t da1, uint32_t da2, int n) { uint32_t vpn = aa & UTLB_AA_VPN; bool pmb = (vpn & 0xc0000000) == 0x80000000; @@ -639,7 +645,7 @@ if (!valid) return; - printf ("(%c|%c) ", aa & UTLB_AA_D ? 'D' : '-', valid ? 'V' : '-'); + printf("(%c|%c) ", aa & UTLB_AA_D ? 'D' : '-', valid ? 'V' : '-'); const char *pmb_pgsz[] = { " 16M", " 64M", "128M", "512M" }; #ifdef SH4A_EXT_MMU const char *pgsz[] = { " 1K", " 4K", " 8K", "-XX-", @@ -652,7 +658,7 @@ sz = (da2 >> 4) & 0xf; if (!pmb) { - printf ("[%c%c%c][%c%c%c] ", + printf("[%c%c%c][%c%c%c] ", da2 & UTLB_DA2_EPR_P_R ? 'r' : '-', da2 & UTLB_DA2_EPR_P_W ? 'w' : '-', da2 & UTLB_DA2_EPR_P_X ? 'x' : '-', @@ -671,31 +677,31 @@ "[rw][--]", "[rw][r-]", "[rw][rw]" }; - printf ("%s ", pr_pat[pr]); + printf("%s ", pr_pat[pr]); } #endif - printf ("%s ", pmb ? pmb_pgsz[sz] : pgsz[sz]); + printf("%s ", pmb ? pmb_pgsz[sz] : pgsz[sz]); #ifdef SH4A_EXT_ADDR32 - printf ("%s ", da1 & UTLB_DA1_UB ? "UB" : "--"); + printf("%s ", da1 & UTLB_DA1_UB ? "UB" : "--"); #endif if (da1 & UTLB_DA1_C) { - printf ("W%c ", da1 & UTLB_DA1_WT ? 'T' : 'B'); + printf("W%c ", da1 & UTLB_DA1_WT ? 'T' : 'B'); } else { - printf ("-- "); + printf("-- "); } bool shared_page = da1 & UTLB_DA1_SH; if (!pmb) - printf ("%s ", shared_page ? "SH" : "--"); - printf ("VPN:%x PPN:%x ", aa & UTLB_AA_VPN, da1 & UTLB_DA1_PPN); + printf("%s ", shared_page ? "SH" : "--"); + printf("VPN:%x PPN:%x ", aa & UTLB_AA_VPN, da1 & UTLB_DA1_PPN); if (pmb) - printf ("PMB "); + printf("PMB "); else if (!shared_page) - printf ("ASID:%x ", aa & UTLB_AA_ASID); + printf("ASID:%x ", aa & UTLB_AA_ASID); - printf ("[%d]\n", n); + printf("[%d]\n", n); } #endif // DEBUG diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/pmap.c src-sh4a/sys/arch/sh3/sh3/pmap.c --- src-sh4a.orig/sys/arch/sh3/sh3/pmap.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/pmap.c 2010-04-06 18:32:32.000000000 +0900 @@ -93,8 +93,7 @@ STATIC pt_entry_t *__pmap_pte_alloc(pmap_t, vaddr_t); /* pmap_enter util */ -STATIC bool __pmap_map_change(pmap_t, vaddr_t, paddr_t, vm_prot_t, - pt_entry_t); +STATIC bool __pmap_map_change(pmap_t, vaddr_t, paddr_t, vm_prot_t, pt_entry_t); void pmap_bootstrap(void) @@ -547,7 +546,7 @@ void pmap_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva) { - printf("%s: asid%d %lx-%lx\n", __FUNCTION__, pmap->pm_asid, sva, eva); +//XXXNONAKA printf("%s: asid%d %lx-%lx\n", __FUNCTION__, pmap->pm_asid, sva, eva); struct vm_page *pg; pt_entry_t *pte, entry; vaddr_t va; @@ -819,11 +818,13 @@ void pmap_zero_page(paddr_t phys) { + struct vm_page *pg; + // printf("%s pa=%lx\n", __FUNCTION__, phys); #ifdef SH4A_EXT_ADDR32 if (phys < 0x20000000) goto maped_area; - struct vm_page *pg; + struct vm_page_md *pvh; struct pv_entry *pv; @@ -866,7 +867,7 @@ void pmap_copy_page(paddr_t src, paddr_t dst) { - printf("%s src:%lx, dst:%lx\n", __FUNCTION__, src, dst); +//XXXNONAKA printf("%s src:%lx, dst:%lx\n", __FUNCTION__, src, dst); struct vm_page *pg; #ifdef SH4A_EXT_ADDR32 if (src < 0x20000000 && dst < 0x20000000) @@ -900,7 +901,7 @@ #endif if (SH_HAS_VIRTUAL_ALIAS) { /* sync cache since we access via P2. */ - printf("%s P2\n", __FUNCTION__); +//XXXNONAKA printf("%s P2\n", __FUNCTION__); if ((pg = PHYS_TO_VM_PAGE(dst))) __pmap_dcache_inv_pg(pg); if ((pg = PHYS_TO_VM_PAGE(src))) @@ -1039,7 +1040,7 @@ printf("%s %lx\n", __FUNCTION__, *vap); assert (!(foff & 0x1f)); if (SH_HAS_VIRTUAL_ALIAS) { -#if 0 +#if 1 va = *vap; *vap = va + ((foff - va) & sh_cache_prefer_mask); #else @@ -1048,7 +1049,6 @@ uint32_t ci1 = va & (0xff << 5); *vap = va + (ci0 - ci1); #endif - } } #endif /* SH_HAS_VIRTUAL_ALIAS */ @@ -1224,8 +1224,8 @@ if ((map & (1 << j)) == 0 && (k + j) != 0) { __pmap_asid.map[k] |= (1 << j); __pmap_asid.hint = (k << 5) + j; - printf("%s: %d\n", __FUNCTION__, - __pmap_asid.hint); +//XXXNONAKA printf("%s: %d\n", __FUNCTION__, +//XXXNONAKA __pmap_asid.hint); return (__pmap_asid.hint); } } @@ -1259,7 +1259,7 @@ if (asid < 1) /* Don't invalidate kernel ASID 0 */ return; - printf("%s:%d\n", __FUNCTION__, asid); +//XXXNONAKA printf("%s:%d\n", __FUNCTION__, asid); sh_tlb_invalidate_asid(asid); // void sh4a_dcache_array_dump (vaddr_t va, vsize_t sz); // sh4a_dcache_array_dump(0, 32*1024); diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/pmap_cache_ops.c src-sh4a/sys/arch/sh3/sh3/pmap_cache_ops.c --- src-sh4a.orig/sys/arch/sh3/sh3/pmap_cache_ops.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/pmap_cache_ops.c 2010-04-06 19:16:02.000000000 +0900 @@ -141,7 +141,7 @@ printf("%s: %p\n", __FUNCTION__, pg); pvh = &pg->mdpage; SLIST_FOREACH(pv, &pvh->pvh_head, pv_link) { - printf ("%p: %p-%lx\n", pg, pv->pv_pmap, pv->pv_va); + printf("%p: %p-%lx\n", pg, pv->pv_pmap, pv->pv_va); } } @@ -150,9 +150,9 @@ int current_asid = sh_tlb_get_asid(); if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) - current_icache_inv(va, PAGE_SIZE); + current_icache_inv(va, PAGE_SIZE); else - noncurrent_icache_inv(va, PAGE_SIZE); + noncurrent_icache_inv(va, PAGE_SIZE); } @@ -161,9 +161,9 @@ int current_asid = sh_tlb_get_asid(); if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) - current_dcache_inv(va, PAGE_SIZE); + current_dcache_inv(va, PAGE_SIZE); else - noncurrent_dcache_inv(va, PAGE_SIZE); + noncurrent_dcache_inv(va, PAGE_SIZE); } void __pmap_dcache_wb_va(struct pmap *pmap, vaddr_t va) @@ -171,9 +171,9 @@ int current_asid = sh_tlb_get_asid(); if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) - current_dcache_wb(va, PAGE_SIZE); + current_dcache_wb(va, PAGE_SIZE); else - noncurrent_dcache_wb(va, PAGE_SIZE); + noncurrent_dcache_wb(va, PAGE_SIZE); } void __pmap_dcache_wbinv_va(struct pmap *pmap, vaddr_t va) @@ -181,15 +181,15 @@ int current_asid = sh_tlb_get_asid(); if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) - current_dcache_wbinv(va, PAGE_SIZE); + current_dcache_wbinv(va, PAGE_SIZE); else - noncurrent_dcache_wbinv(va, PAGE_SIZE); + noncurrent_dcache_wbinv(va, PAGE_SIZE); } extern int __tlb_exception_cnt; extern int __tlb_exception_debug; -paddr_t sh4a_mmu_utlb_lookup_by_va (vaddr_t); -void sh4a_dcache_array_dump (vaddr_t, vsize_t); +paddr_t sh4a_mmu_utlb_lookup_by_va(vaddr_t); +void sh4a_dcache_array_dump(vaddr_t, vsize_t); void __pmap_dcache_inv_pg(struct vm_page *pg) { @@ -201,9 +201,9 @@ // int s = splvm(); SLIST_FOREACH(pv, &pvh->pvh_head, pv_link) { pmap = pv->pv_pmap; - paddr_t pa = sh4a_mmu_utlb_lookup_by_va (pv->pv_va); -// sh4a_dcache_array_dump (pv->pv_va, PAGE_SIZE); - printf("%s: ASID%d<->%d %p,va:%lx pa:%lx ", __FUNCTION__, current_asid, pmap->pm_asid, pmap, pv->pv_va, pa); +//XXXNONAKA paddr_t pa = sh4a_mmu_utlb_lookup_by_va(pv->pv_va); +// sh4a_dcache_array_dump(pv->pv_va, PAGE_SIZE); +//XXXNONAKA printf("%s: ASID%d<->%d %p,va:%lx pa:%lx ", __FUNCTION__, current_asid, pmap->pm_asid, pmap, pv->pv_va, pa); if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) { printf("ohayo0 %d\n", __tlb_exception_cnt); __tlb_exception_debug = 1; @@ -211,7 +211,7 @@ printf("ohayo1 %d\n", __tlb_exception_cnt); __tlb_exception_debug = 0; } else { - noncurrent_dcache_inv(pv->pv_va, PAGE_SIZE); + noncurrent_dcache_inv(pv->pv_va, PAGE_SIZE); } } // splx(s); @@ -228,9 +228,9 @@ SLIST_FOREACH(pv, &pvh->pvh_head, pv_link) { pmap = pv->pv_pmap; if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) - current_dcache_wb(pv->pv_va, PAGE_SIZE); + current_dcache_wb(pv->pv_va, PAGE_SIZE); else - noncurrent_dcache_wb(pv->pv_va, PAGE_SIZE); + noncurrent_dcache_wb(pv->pv_va, PAGE_SIZE); } } @@ -244,7 +244,7 @@ pvh = &pg->mdpage; SLIST_FOREACH(pv, &pvh->pvh_head, pv_link) { pmap = pv->pv_pmap; - printf("%s: ASID%d<->%d %p,va:%lx pa:%lx ", __FUNCTION__, current_asid, pmap->pm_asid, pmap, pv->pv_va, sh4a_mmu_utlb_lookup_by_va (pv->pv_va)); +//XXXNONAKA printf("%s: ASID%d<->%d %p,va:%lx pa:%lx ", __FUNCTION__, current_asid, pmap->pm_asid, pmap, pv->pv_va, sh4a_mmu_utlb_lookup_by_va (pv->pv_va)); if (pmap == pmap_kernel() || pmap->pm_asid == current_asid) { // printf("ohayo-0 %d\n", __tlb_exception_cnt); current_dcache_wbinv(pv->pv_va, PAGE_SIZE); diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/pmap_map_poolpage.c src-sh4a/sys/arch/sh3/sh3/pmap_map_poolpage.c --- src-sh4a.orig/sys/arch/sh3/sh3/pmap_map_poolpage.c 2010-01-06 19:11:51.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/pmap_map_poolpage.c 2010-03-28 18:32:45.000000000 +0900 @@ -1,4 +1,3 @@ -#if 0 vaddr_t pmap_map_poolpage(paddr_t pa) { @@ -14,7 +13,7 @@ pvh = &pg->mdpage; if ((pv = SLIST_FIRST(&pvh->pvh_head)) != 0) return pv->pv_va; - panic(__FUNCTION__); + assert(kernel_map); uvm_flag_t mapflags = UVM_MAPFLAG(UVM_PROT_ALL, UVM_PROT_ALL, UVM_INH_NONE, UVM_ADV_RANDOM, UVM_FLAG_NOMERGE); @@ -23,10 +22,10 @@ UVM_UNKNOWN_OFFSET, 0, mapflags, &args); vaddr_t va = args.uma_start; - printf ("%s pa=%lx va=%lx\n", __FUNCTION__, pa, va); + printf ("%s: pa=%lx va=%lx\n", __FUNCTION__, pa, va); pmap_kenter_pa(va, VM_PAGE_TO_PHYS(pg), - VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE); + VM_PROT_READ|VM_PROT_WRITE|PMAP_KMPAGE, 0); vm_map_unlock(kernel_map); return va; @@ -40,7 +39,5 @@ pmap_extract(&__pmap_kernel, va, &pa); if (pa < 0x20000000) return SH3_P1SEG_TO_PHYS(va); - panic(__FUNCTION__); return pa; } -#endif diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/arch/sh3/sh3/sh3_machdep.c src-sh4a/sys/arch/sh3/sh3/sh3_machdep.c --- src-sh4a.orig/sys/arch/sh3/sh3/sh3_machdep.c 2010-03-22 20:34:31.000000000 +0900 +++ src-sh4a/sys/arch/sh3/sh3/sh3_machdep.c 2010-04-06 18:30:52.000000000 +0900 @@ -87,8 +87,6 @@ #include #include -#include //for mb_map - #ifdef KGDB #include #ifndef KGDB_DEVNAME @@ -222,7 +220,7 @@ /* * u-area map: - * |pcb| .... | .................. | + * | pcb | ... | .................. | * | PAGE_SIZE | USPACE - PAGE_SIZE | * frame bot stack bot * current frame ... r6_bank @@ -267,7 +265,7 @@ sh4_vector_tlbmiss_end - sh4_vector_tlbmiss #elif defined(SH3) sh3_vector_tlbmiss_end - sh3_vector_tlbmiss -#elif defined(SH4) || defined (SH4A) +#elif defined(SH4) || defined(SH4A) sh4_vector_tlbmiss_end - sh4_vector_tlbmiss #endif ); @@ -286,9 +284,6 @@ phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, VM_PHYS_SIZE, 0, false, NULL); - mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, - nmbclusters * mclbytes, VM_MAP_INTRSAFE, false, NULL); - format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); printf("avail memory = %s\n", pbuf); } diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/dev/ic/rtl8169.c src-sh4a/sys/dev/ic/rtl8169.c --- src-sh4a.orig/sys/dev/ic/rtl8169.c 2010-02-20 18:40:20.000000000 +0900 +++ src-sh4a/sys/dev/ic/rtl8169.c 2010-04-06 16:32:12.000000000 +0900 @@ -570,6 +570,7 @@ case RTK_HWREV_8169S: case RTK_HWREV_8110S: case RTK_HWREV_8169_8110SB: + case RTK_HWREV_8169_8110SBL: case RTK_HWREV_8169_8110SC: sc->sc_quirk |= RTKQ_MACLDPS; break; @@ -812,6 +813,11 @@ callout_init(&sc->rtk_tick_ch, 0); +#if 1 // XXXNONAKA from OpenBSD + re_gmii_writereg(sc->sc_dev, 1, 0x1f, 0); + re_gmii_writereg(sc->sc_dev, 1, 0x0e, 0); +#endif + /* Do MII setup */ sc->mii.mii_ifp = ifp; sc->mii.mii_readreg = re_miibus_readreg; diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/dev/ic/rtl81x9reg.h src-sh4a/sys/dev/ic/rtl81x9reg.h --- src-sh4a.orig/sys/dev/ic/rtl81x9reg.h 2009-09-17 19:38:44.000000000 +0900 +++ src-sh4a/sys/dev/ic/rtl81x9reg.h 2010-03-21 20:12:34.000000000 +0900 @@ -181,6 +181,7 @@ #define RTK_HWREV_8139CPLUS 0x74800000 #define RTK_HWREV_8101 0x74c00000 #define RTK_HWREV_8100 0x78800000 +#define RTK_HWREV_8169_8110SBL 0x7cc00000 #define RTK_TXDMA_16BYTES 0x00000000 #define RTK_TXDMA_32BYTES 0x00000100 diff --exclude=CVS --exclude=obj.evbsh3 --exclude=compile --exclude='makeBuild*.log' -uNr src-sh4a.orig/sys/kern/kern_synch.c src-sh4a/sys/kern/kern_synch.c --- src-sh4a.orig/sys/kern/kern_synch.c 2010-03-06 06:04:28.000000000 +0900 +++ src-sh4a/sys/kern/kern_synch.c 2010-04-06 16:40:49.000000000 +0900 @@ -776,6 +776,12 @@ (*dtrace_vtime_switch_func)(newl); } +#if 1 // XXXNONAKA + volatile int t1 = l->l_md.md_pcb->pcb_sf.sf_gbr; + volatile int t2 = newl->l_md.md_pcb->pcb_sf.sf_gbr; + (void) t1; + (void) t2; +#endif /* Switch to the new LWP.. */ prevlwp = cpu_switchto(l, newl, returning); ci = curcpu(); @@ -926,6 +932,10 @@ (*dtrace_vtime_switch_func)(newl); } +#if 1 // XXXNONAKA + volatile int t = newl->l_md.md_pcb->pcb_sf.sf_gbr; + (void) t; +#endif /* Switch to the new LWP.. */ (void)cpu_switchto(NULL, newl, false);