NEON Intrinsics
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Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
FADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPAdd(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
FADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPAdd(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
FADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPAdd(element1, element2, FPCR); V[d] = result;
A64
Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
FADD Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPAdd(element1, element2, FPCR); V[d] = result;
A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
A64
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
ADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
A64
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
SADDL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
SADDL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
SADDL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UADDL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UADDL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UADDL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
SADDL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
SADDL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
SADDL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UADDL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UADDL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UADDL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
SADDW Vd.8H,Vn.8H,Vm.8B
a → Vn.8H
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
SADDW Vd.4S,Vn.4S,Vm.4H
a → Vn.4S
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
SADDW Vd.2D,Vn.2D,Vm.2S
a → Vn.2D
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
UADDW Vd.8H,Vn.8H,Vm.8B
a → Vn.8H
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
UADDW Vd.4S,Vn.4S,Vm.4H
a → Vn.4S
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
UADDW Vd.2D,Vn.2D,Vm.2S
a → Vn.2D
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
SADDW2 Vd.8H,Vn.8H,Vm.16B
a → Vn.8H
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
SADDW2 Vd.4S,Vn.4S,Vm.8H
a → Vn.4S
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
SADDW2 Vd.2D,Vn.2D,Vm.4S
a → Vn.2D
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
UADDW2 Vd.8H,Vn.8H,Vm.16B
a → Vn.8H
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
UADDW2 Vd.4S,Vn.4S,Vm.8H
a → Vn.4S
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
UADDW2 Vd.2D,Vn.2D,Vm.4S
a → Vn.2D
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SHADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SHADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SHADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SHADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SHADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SHADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UHADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UHADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UHADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UHADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UHADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UHADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; Elem[result, e, esize] = sum<esize:1>; V[d] = result;
v7/A32/A64
Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SRHADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SRHADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SRHADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SRHADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SRHADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SRHADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
URHADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
URHADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
URHADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
URHADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
URHADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.
URHADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, esize] = (element1+element2+1)<esize:1>; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQADD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer sum; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); sum = element1 + element2; (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.8B,Vn.8B
a → Vd.8B
b → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.16B,Vn.16B
a → Vd.16B
b → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.4H,Vn.4H
a → Vd.4H
b → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.8H,Vn.8H
a → Vd.8H
b → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.2S,Vn.2S
a → Vd.2S
b → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.4S,Vn.4S
a → Vd.4S
b → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Dd,Dn
a → Dd
b → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Vd.2D,Vn.2D
a → Vd.2D
b → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Bd,Bn
a → Bd
b → Bn
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Hd,Hn
a → Hd
b → Hn
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Sd,Sn
a → Sd
b → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.
SUQADD Dd,Dn
a → Dd
b → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.8B,Vn.8B
a → Vd.8B
b → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.16B,Vn.16B
a → Vd.16B
b → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.4H,Vn.4H
a → Vd.4H
b → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.8H,Vn.8H
a → Vd.8H
b → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.2S,Vn.2S
a → Vd.2S
b → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.4S,Vn.4S
a → Vd.4S
b → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Dd,Dn
a → Dd
b → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Vd.2D,Vn.2D
a → Vd.2D
b → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Bd,Bn
a → Bd
b → Bn
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Hd,Hn
a → Hd
b → Hn
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Sd,Sn
a → Sd
b → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.
USQADD Dd,Dn
a → Dd
b → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
ADDHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RADDHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
MUL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.
FMUL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.
FMUL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
PMUL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
PMUL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if poly then product = PolynomialMult(element1, element2)<esize-1:0>; else product = (UInt(element1)*UInt(element2))<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;
v7/A32/A64
Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.
FMUL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.
FMUL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.2S,Vn.2S,Vm.S[lane]
a → Vn.2S
v → Vm.2S
0 << lane << 1
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.4S,Vn.4S,Vm.S[lane]
a → Vn.4S
v → Vm.2S
0 << lane << 1
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Dd,Dn,Vm.D[lane]
a → Dn
v → Vm.1D
0 << lane << 0
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.2D,Vn.2D,Vm.D[lane]
a → Vn.2D
v → Vm.1D
0 << lane << 0
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Sd,Sn,Vm.S[lane]
a → Sn
v → Vm.2S
0 << lane << 1
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Dd,Dn,Vm.D[lane]
a → Dn
v → Vm.1D
0 << lane << 0
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.2S,Vn.2S,Vm.S[lane]
a → Vn.2S
v → Vm.4S
0 << lane << 3
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.4S,Vn.4S,Vm.S[lane]
a → Vn.4S
v → Vm.4S
0 << lane << 3
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Dd,Dn,Vm.D[lane]
a → Dn
v → Vm.2D
0 << lane << 1
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Vd.2D,Vn.2D,Vm.D[lane]
a → Vn.2D
v → Vm.2D
0 << lane << 1
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Sd,Sn,Vm.S[lane]
a → Sn
v → Vm.4S
0 << lane << 3
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FMULX Dd,Dn,Vm.D[lane]
a → Dn
v → Vm.2D
0 << lane << 1
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
A64
Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FDIV Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPDiv(element1, element2, FPCR); V[d] = result;
A64
Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FDIV Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPDiv(element1, element2, FPCR); V[d] = result;
A64
Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FDIV Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPDiv(element1, element2, FPCR); V[d] = result;
A64
Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
FDIV Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = FPDiv(element1, element2, FPCR); V[d] = result;
A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.8B,Vn.8B,Vm.8B
a → Vd.8B
b → Vn.8B
c → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.16B,Vn.16B,Vm.16B
a → Vd.16B
b → Vn.16B
c → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.4H,Vn.4H,Vm.4H
a → Vd.4H
b → Vn.4H
c → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.8H,Vn.8H,Vm.8H
a → Vd.8H
b → Vn.8H
c → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.8B,Vn.8B,Vm.8B
a → Vd.8B
b → Vn.8B
c → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.16B,Vn.16B,Vm.16B
a → Vd.16B
b → Vn.16B
c → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.4H,Vn.4H,Vm.4H
a → Vd.4H
b → Vn.4H
c → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.8H,Vn.8H,Vm.8H
a → Vd.8H
b → Vn.8H
c → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.
MLA Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
a → N/A
b → N/A
c → N/A
N/A → result
v7/A32/A64
RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3
a → N/A
b → N/A
c → N/A
N/A → result
v7/A32/A64
RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
a → N/A
b → N/A
c → N/A
N/A → result
A64
RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
a → N/A
b → N/A
c → N/A
N/A → result
A64
Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLAL Vd.8H,Vn.8B,Vm.8B
a → Vd.8H
b → Vn.8B
c → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLAL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLAL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
UMLAL Vd.8H,Vn.8B,Vm.8B
a → Vd.8H
b → Vn.8B
c → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
UMLAL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
UMLAL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLAL2 Vd.8H,Vn.16B,Vm.16B
a → Vd.8H
b → Vn.16B
c → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLAL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLAL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
UMLAL2 Vd.8H,Vn.16B,Vm.16B
a → Vd.8H
b → Vn.16B
c → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
UMLAL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
UMLAL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.8B,Vn.8B,Vm.8B
a → Vd.8B
b → Vn.8B
c → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.16B,Vn.16B,Vm.16B
a → Vd.16B
b → Vn.16B
c → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.4H,Vn.4H,Vm.4H
a → Vd.4H
b → Vn.4H
c → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.8H,Vn.8H,Vm.8H
a → Vd.8H
b → Vn.8H
c → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.8B,Vn.8B,Vm.8B
a → Vd.8B
b → Vn.8B
c → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.16B,Vn.16B,Vm.16B
a → Vd.16B
b → Vn.16B
c → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.4H,Vn.4H,Vm.4H
a → Vd.4H
b → Vn.4H
c → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.8H,Vn.8H,Vm.8H
a → Vd.8H
b → Vn.8H
c → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.
MLS Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) product; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; product = (UInt(element1)*UInt(element2))<esize-1:0>; if sub_op then Elem[result, e, esize] = Elem[operand3, e, esize] - product; else Elem[result, e, esize] = Elem[operand3, e, esize] + product; V[d] = result;
v7/A32/A64
RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
a → N/A
b → N/A
c → N/A
N/A → result
v7/A32/A64
RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3
a → N/A
b → N/A
c → N/A
N/A → result
v7/A32/A64
RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
a → N/A
b → N/A
c → N/A
N/A → result
A64
RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
a → N/A
b → N/A
c → N/A
N/A → result
A64
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLSL Vd.8H,Vn.8B,Vm.8B
a → Vd.8H
b → Vn.8B
c → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLSL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLSL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMLSL Vd.8H,Vn.8B,Vm.8B
a → Vd.8H
b → Vn.8B
c → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMLSL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMLSL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
v7/A32/A64
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLSL2 Vd.8H,Vn.16B,Vm.16B
a → Vd.8H
b → Vn.16B
c → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLSL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SMLSL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMLSL2 Vd.8H,Vn.16B,Vm.16B
a → Vd.8H
b → Vn.16B
c → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMLSL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMLSL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.
FMADD Dd,Dn,Dm,Da
a → Da
b → Dn
c → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) result; bits(datasize) operanda = V[a]; bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; result = FPMulAdd(operanda, operand1, operand2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.2D,Vn.2D,Vm.2D
a → Vd.2D
b → Vn.2D
c → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.2S,Vn.2S,Vm.S[lane]
a → Vd.2S
b → Vn.2S
v → Vm.2S
0 << lane << 1
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.4S,Vn.4S,Vm.S[lane]
a → Vd.4S
b → Vn.4S
v → Vm.2S
0 << lane << 1
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.1D
0 << lane << 0
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.2D,Vn.2D,Vm.D[lane]
a → Vd.2D
b → Vn.2D
v → Vm.1D
0 << lane << 0
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Sd,Sn,Vm.S[lane]
a → Sd
b → Sn
v → Vm.2S
0 << lane << 1
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.1D
0 << lane << 0
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.2S,Vn.2S,Vm.S[lane]
a → Vd.2S
b → Vn.2S
v → Vm.4S
0 << lane << 3
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.4S,Vn.4S,Vm.S[lane]
a → Vd.4S
b → Vn.4S
v → Vm.4S
0 << lane << 3
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.2D
0 << lane << 1
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Vd.2D,Vn.2D,Vm.D[lane]
a → Vd.2D
b → Vn.2D
v → Vm.2D
0 << lane << 1
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Sd,Sn,Vm.S[lane]
a → Sd
b → Sn
v → Vm.4S
0 << lane << 3
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLA Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.2D
0 << lane << 1
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.
FMSUB Dd,Dn,Dm,Da
a → Da
b → Dn
c → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) result; bits(datasize) operanda = V[a]; bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; operand1 = FPNeg(operand1); result = FPMulAdd(operanda, operand1, operand2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.2D,Vn.2D,Vm.2D
a → Vd.2D
b → Vn.2D
c → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.2S,Vn.2S,Vm.S[lane]
a → Vd.2S
b → Vn.2S
v → Vm.2S
0 << lane << 1
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.4S,Vn.4S,Vm.S[lane]
a → Vd.4S
b → Vn.4S
v → Vm.2S
0 << lane << 1
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.1D
0 << lane << 0
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.2D,Vn.2D,Vm.D[lane]
a → Vd.2D
b → Vn.2D
v → Vm.1D
0 << lane << 0
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Sd,Sn,Vm.S[lane]
a → Sd
b → Sn
v → Vm.2S
0 << lane << 1
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.1D
0 << lane << 0
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.2S,Vn.2S,Vm.S[lane]
a → Vd.2S
b → Vn.2S
v → Vm.4S
0 << lane << 3
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.4S,Vn.4S,Vm.S[lane]
a → Vd.4S
b → Vn.4S
v → Vm.4S
0 << lane << 3
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.2D
0 << lane << 1
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Vd.2D,Vn.2D,Vm.D[lane]
a → Vd.2D
b → Vn.2D
v → Vm.2D
0 << lane << 1
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Sd,Sn,Vm.S[lane]
a → Sd
b → Sn
v → Vm.4S
0 << lane << 3
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
FMLS Dd,Dn,Vm.D[lane]
a → Dd
b → Dn
v → Vm.2D
0 << lane << 1
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR); V[d] = result;
A64
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQDMULH Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQDMULH Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQDMULH Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQDMULH Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQDMULH Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQDMULH Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQRDMULH Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQRDMULH Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQRDMULH Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQRDMULH Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQRDMULH Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
SQRDMULH Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); product = (2 * element1 * element2) + round_const; (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLAL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLAL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLAL Sd,Hn,Hm
a → Sd
b → Hn
c → Hm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLAL Dd,Sn,Sm
a → Dd
b → Sn
c → Sm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLAL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLAL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLSL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLSL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLSL Sd,Hn,Hm
a → Sd
b → Hn
c → Hm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLSL Dd,Sn,Sm
a → Dd
b → Sn
c → Sm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLSL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
SQDMLSL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; integer accum; boolean sat1; boolean sat2; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize); if sub_op then accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product); else accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product); (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize); if sat1 || sat2 then FPSR.QC = '1'; V[d] = result;
A64
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SMULL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SMULL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SMULL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMULL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMULL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMULL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
v7/A32/A64
Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
PMULL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, 2*esize] = PolynomialMult(element1, element2); V[d] = result;
v7/A32/A64
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SMULL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
A64
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SMULL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
A64
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SMULL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
A64
Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMULL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
A64
Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMULL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
A64
Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.
UMULL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>; V[d] = result;
A64
Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
PMULL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, 2*esize] = PolynomialMult(element1, element2); V[d] = result;
A64
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
SQDMULL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize); Elem[result, e, 2*esize] = product; if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
SQDMULL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize); Elem[result, e, 2*esize] = product; if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
SQDMULL Sd,Hn,Hm
a → Hn
b → Hm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize); Elem[result, e, 2*esize] = product; if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
SQDMULL Dd,Sn,Sm
a → Sn
b → Sm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize); Elem[result, e, 2*esize] = product; if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
SQDMULL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize); Elem[result, e, 2*esize] = product; if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.
SQDMULL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize); Elem[result, e, 2*esize] = product; if sat then FPSR.QC = '1'; V[d] = result;
A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
v7/A32/A64
Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
FSUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
v7/A32/A64
Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
FSUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
v7/A32/A64
Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
FSUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
A64
Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
FSUB Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
A64
Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.
SUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if sub_op then Elem[result, e, esize] = element1 - element2; else Elem[result, e, esize] = element1 + element2; V[d] = result;
A64
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.
SSUBL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.
SSUBL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.
SSUBL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.
USUBL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.
USUBL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.
USUBL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.
SSUBL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.
SSUBL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.
SSUBL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.
USUBL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.
USUBL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.
USUBL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
SSUBW Vd.8H,Vn.8H,Vm.8B
a → Vn.8H
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
SSUBW Vd.4S,Vn.4S,Vm.4H
a → Vn.4S
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
SSUBW Vd.2D,Vn.2D,Vm.2S
a → Vn.2D
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
USUBW Vd.8H,Vn.8H,Vm.8B
a → Vn.8H
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
USUBW Vd.4S,Vn.4S,Vm.4H
a → Vn.4S
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
USUBW Vd.2D,Vn.2D,Vm.2S
a → Vn.2D
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
v7/A32/A64
Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
SSUBW2 Vd.8H,Vn.8H,Vm.16B
a → Vn.8H
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
SSUBW2 Vd.4S,Vn.4S,Vm.8H
a → Vn.4S
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
SSUBW2 Vd.2D,Vn.2D,Vm.4S
a → Vn.2D
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
USUBW2 Vd.8H,Vn.8H,Vm.16B
a → Vn.8H
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
USUBW2 Vd.4S,Vn.4S,Vm.8H
a → Vn.4S
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.
USUBW2 Vd.2D,Vn.2D,Vm.4S
a → Vn.2D
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, 2*esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); if sub_op then sum = element1 - element2; else sum = element1 + element2; Elem[result, e, 2*esize] = sum<2*esize-1:0>; V[d] = result;
A64
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
SHSUB Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
SHSUB Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
SHSUB Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
SHSUB Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
SHSUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
SHSUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.
UHSUB Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.
UHSUB Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.
UHSUB Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.
UHSUB Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.
UHSUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.
UHSUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; Elem[result, e, esize] = diff<esize:1>; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQSUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQSUB Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.
SUBHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN Vd.8B,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN Vd.4H,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN Vd.2S,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
v7/A32/A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN2 Vd.16B,Vn.8H,Vm.8H
r → Vd.8B
a → Vn.8H
b → Vm.8H
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN2 Vd.8H,Vn.4S,Vm.4S
r → Vd.4H
a → Vn.4S
b → Vm.4S
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
RSUBHN2 Vd.4S,Vn.2D,Vm.2D
r → Vd.2S
a → Vn.2D
b → Vm.2D
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand1 = V[n]; bits(2*datasize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; bits(2*esize) element1; bits(2*esize) element2; bits(2*esize) sum; for e = 0 to elements-1 element1 = Elem[operand1, e, 2*esize]; element2 = Elem[operand2, e, 2*esize]; if sub_op then sum = element1 - element2; else sum = element1 + element2; sum = sum + round_const; Elem[result, e, esize] = sum<2*esize-1:esize>; Vpart[d, part] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A32/A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4H,Vn.4H,#0
a → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8H,Vn.8H,#0
a → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4H,Vn.4H,#0
a → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8H,Vn.8H,#0
a → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A32/A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A32/A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Sd,Sn,#0
a → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMEQ Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.8B,Vm.8B,Vn.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.16B,Vm.16B,Vn.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.4H,Vm.4H,Vn.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.8H,Vm.8H,Vn.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.8B,Vm.8B,Vn.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.16B,Vm.16B,Vn.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.4H,Vm.4H,Vn.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.8H,Vm.8H,Vn.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.4H,Vn.4H,#0
a → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.8H,Vn.8H,#0
a → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Sd,Sn,#0
a → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.8B,Vm.8B,Vn.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.16B,Vm.16B,Vn.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.4H,Vm.4H,Vn.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.8H,Vm.8H,Vn.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.8B,Vm.8B,Vn.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.16B,Vm.16B,Vn.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.4H,Vm.4H,Vn.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.8H,Vm.8H,Vn.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGE Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHS Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Sd,Sm,Sn
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGE Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.4H,Vn.4H,#0
a → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.8H,Vn.8H,#0
a → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLE Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLE Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLE Sd,Sn,#0
a → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLE Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.4H,Vn.4H,#0
a → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.8H,Vn.8H,#0
a → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Sd,Sn,#0
a → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.8B,Vm.8B,Vn.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.16B,Vm.16B,Vn.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.4H,Vm.4H,Vn.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.8H,Vm.8H,Vn.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.8B,Vm.8B,Vn.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.16B,Vm.16B,Vn.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.4H,Vm.4H,Vn.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.8H,Vm.8H,Vn.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMGT Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMHI Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; boolean test_passed; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); test_passed = if cmp_eq then element1 >= element2 else element1 > element2; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Sd,Sm,Sn
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMGT Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.8B,Vn.8B,#0
a → Vn.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.16B,Vn.16B,#0
a → Vn.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.4H,Vn.4H,#0
a → Vn.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.8H,Vn.8H,#0
a → Vn.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLT Vd.2S,Vn.2S,#0
a → Vn.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLT Vd.4S,Vn.4S,#0
a → Vn.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLT Vd.2D,Vn.2D,#0
a → Vn.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMLT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLT Sd,Sn,#0
a → Sn
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FCMLT Dd,Dn,#0
a → Dn
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) zero = FPZero('0'); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Vd.2D,Vm.2D,Vn.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Sd,Sm,Sn
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGE Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Vd.2S,Vm.2S,Vn.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Vd.4S,Vm.4S,Vn.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Sd,Sm,Sn
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
FACGT Dd,Dm,Dn
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
v7/A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A32/A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
CMTST Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if and_test then test_passed = !IsZero(element1 AND element2); else test_passed = (element1 == element2); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
A64
Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
SABD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
SABD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
SABD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
SABD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
SABD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
SABD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
UABD Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
UABD Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
UABD Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
UABD Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
UABD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.
UABD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.
FABD Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
v7/A32/A64
Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.
FABD Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
v7/A32/A64
Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.
FABD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
A64
Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.
FABD Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
A64
Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.
FABD Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
A64
Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.
FABD Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) diff; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; diff = FPSub(element1, element2, FPCR); Elem[result, e, esize] = if abs then FPAbs(diff) else diff; V[d] = result;
A64
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABDL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABDL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABDL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABDL Vd.8H,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABDL Vd.4S,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABDL Vd.2D,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABDL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABDL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABDL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABDL2 Vd.8H,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABDL2 Vd.4S,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABDL2 Vd.2D,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
SABA Vd.8B,Vn.8B,Vm.8B
a → Vd.8B
b → Vn.8B
c → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
SABA Vd.16B,Vn.16B,Vm.16B
a → Vd.16B
b → Vn.16B
c → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
SABA Vd.4H,Vn.4H,Vm.4H
a → Vd.4H
b → Vn.4H
c → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
SABA Vd.8H,Vn.8H,Vm.8H
a → Vd.8H
b → Vn.8H
c → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
SABA Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
SABA Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
UABA Vd.8B,Vn.8B,Vm.8B
a → Vd.8B
b → Vn.8B
c → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
UABA Vd.16B,Vn.16B,Vm.16B
a → Vd.16B
b → Vn.16B
c → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
UABA Vd.4H,Vn.4H,Vm.4H
a → Vd.4H
b → Vn.4H
c → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
UABA Vd.8H,Vn.8H,Vm.8H
a → Vd.8H
b → Vn.8H
c → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
UABA Vd.2S,Vn.2S,Vm.2S
a → Vd.2S
b → Vn.2S
c → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.
UABA Vd.4S,Vn.4S,Vm.4S
a → Vd.4S
b → Vn.4S
c → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABAL Vd.8H,Vn.8B,Vm.8B
a → Vd.8H
b → Vn.8B
c → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABAL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABAL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABAL Vd.8H,Vn.8B,Vm.8B
a → Vd.8H
b → Vn.8B
c → Vm.8B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABAL Vd.4S,Vn.4H,Vm.4H
a → Vd.4S
b → Vn.4H
c → Vm.4H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABAL Vd.2D,Vn.2S,Vm.2S
a → Vd.2D
b → Vn.2S
c → Vm.2S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
v7/A32/A64
Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABAL2 Vd.8H,Vn.16B,Vm.16B
a → Vd.8H
b → Vn.16B
c → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABAL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
SABAL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABAL2 Vd.8H,Vn.16B,Vm.16B
a → Vd.8H
b → Vn.16B
c → Vm.16B
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABAL2 Vd.4S,Vn.8H,Vm.8H
a → Vd.4S
b → Vn.8H
c → Vm.8H
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
UABAL2 Vd.2D,Vn.4S,Vm.4S
a → Vd.2D
b → Vn.4S
c → Vm.4S
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) absdiff; result = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); absdiff = Abs(element1-element2)<2*esize-1:0>; Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff; V[d] = result;
A64
Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMAX Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMAX Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMAX Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMAX Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMAX Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMAX Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMAX Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMAX Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMAX Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMAX Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMAX Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMAX Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAX Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAX Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAX Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
A64
Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAX Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
A64
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMIN Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMIN Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMIN Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMIN Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMIN Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.
SMIN Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMIN Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMIN Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMIN Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMIN Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMIN Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.
UMIN Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer maxmin; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); maxmin = if minimum then Min(element1, element2) else Max(element1, element2); Elem[result, e, esize] = maxmin<esize-1:0>; V[d] = result;
v7/A32/A64
Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMIN Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMIN Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
v7/A32/A64
Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMIN Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
A64
Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMIN Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMin(element1, element2, FPCR); else Elem[result, e, esize] = FPMax(element1, element2, FPCR); V[d] = result;
A64
Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAXNM Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A32/A64
Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAXNM Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A32/A64
Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAXNM Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A64
Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMAXNM Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A64
Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMINNM Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A32/A64
Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMINNM Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A32/A64
Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMINNM Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A64
Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.
FMINNM Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(2*datasize) concat = operand2:operand1; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if pair then element1 = Elem[concat, 2*e, esize]; element2 = Elem[concat, (2*e)+1, esize]; else element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if minimum then Elem[result, e, esize] = FPMinNum(element1, element2, FPCR); else Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR); V[d] = result;
A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
USHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SRSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
URSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.8B,Vn.8B,Vm.8B
a → Vn.8B
b → Vm.8B
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.16B,Vn.16B,Vm.16B
a → Vn.16B
b → Vm.16B
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.4H,Vn.4H,Vm.4H
a → Vn.4H
b → Vm.4H
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.8H,Vn.8H,Vm.8H
a → Vn.8H
b → Vm.8H
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.2S,Vn.2S,Vm.2S
a → Vn.2S
b → Vm.2S
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.4S,Vn.4S,Vm.4S
a → Vn.4S
b → Vm.4S
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Vd.2D,Vn.2D,Vm.2D
a → Vn.2D
b → Vm.2D
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
SQRSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Bd,Bn,Bm
a → Bn
b → Bm
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Hd,Hn,Hm
a → Hn
b → Hm
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Sd,Sn,Sm
a → Sn
b → Sm
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
UQRSHL Dd,Dn,Dm
a → Dn
b → Dm
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.8B,Vn.8B,#n
a → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.16B,Vn.16B,#n
a → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.4H,Vn.4H,#n
a → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.8H,Vn.8H,#n
a → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.2S,Vn.2S,#n
a → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.4S,Vn.4S,#n
a → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Vd.2D,Vn.2D,#n
a → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.8B,Vn.8B,#n
a → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.16B,Vn.16B,#n
a → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.4H,Vn.4H,#n
a → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.8H,Vn.8H,#n
a → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.2S,Vn.2S,#n
a → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.4S,Vn.4S,#n
a → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Vd.2D,Vn.2D,#n
a → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.
SSHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
USHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.8B,Vn.8B,#n
a → Vn.8B
0 << n << 7
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.16B,Vn.16B,#n
a → Vn.16B
0 << n << 7
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.4H,Vn.4H,#n
a → Vn.4H
0 << n << 15
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.8H,Vn.8H,#n
a → Vn.8H
0 << n << 15
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.2S,Vn.2S,#n
a → Vn.2S
0 << n << 31
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.4S,Vn.4S,#n
a → Vn.4S
0 << n << 31
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.2D,Vn.2D,#n
a → Vn.2D
0 << n << 63
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.8B,Vn.8B,#n
a → Vn.8B
0 << n << 7
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.16B,Vn.16B,#n
a → Vn.16B
0 << n << 7
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.4H,Vn.4H,#n
a → Vn.4H
0 << n << 15
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.8H,Vn.8H,#n
a → Vn.8H
0 << n << 15
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.2S,Vn.2S,#n
a → Vn.2S
0 << n << 31
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.4S,Vn.4S,#n
a → Vn.4S
0 << n << 31
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Vd.2D,Vn.2D,#n
a → Vn.2D
0 << n << 63
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
v7/A32/A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
A64
Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.
SHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift); V[d] = result;
A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.8B,Vn.8B,#n
a → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.16B,Vn.16B,#n
a → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.4H,Vn.4H,#n
a → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.8H,Vn.8H,#n
a → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.2S,Vn.2S,#n
a → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.4S,Vn.4S,#n
a → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Vd.2D,Vn.2D,#n
a → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.8B,Vn.8B,#n
a → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.16B,Vn.16B,#n
a → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.4H,Vn.4H,#n
a → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.8H,Vn.8H,#n
a → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.2S,Vn.2S,#n
a → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.4S,Vn.4S,#n
a → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Vd.2D,Vn.2D,#n
a → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.
SRSHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.
URSHR Dd,Dn,#n
a → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.8B,Vn.8B,#n
a → Vd.8B
b → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.16B,Vn.16B,#n
a → Vd.16B
b → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.4H,Vn.4H,#n
a → Vd.4H
b → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.8H,Vn.8H,#n
a → Vd.8H
b → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.2S,Vn.2S,#n
a → Vd.2S
b → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.4S,Vn.4S,#n
a → Vd.4S
b → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Vd.2D,Vn.2D,#n
a → Vd.2D
b → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.8B,Vn.8B,#n
a → Vd.8B
b → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.16B,Vn.16B,#n
a → Vd.16B
b → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.4H,Vn.4H,#n
a → Vd.4H
b → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.8H,Vn.8H,#n
a → Vd.8H
b → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.2S,Vn.2S,#n
a → Vd.2S
b → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.4S,Vn.4S,#n
a → Vd.4S
b → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Vd.2D,Vn.2D,#n
a → Vd.2D
b → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
SSRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.
USRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.8B,Vn.8B,#n
a → Vd.8B
b → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.16B,Vn.16B,#n
a → Vd.16B
b → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.4H,Vn.4H,#n
a → Vd.4H
b → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.8H,Vn.8H,#n
a → Vd.8H
b → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.2S,Vn.2S,#n
a → Vd.2S
b → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.4S,Vn.4S,#n
a → Vd.4S
b → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Vd.2D,Vn.2D,#n
a → Vd.2D
b → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.8B,Vn.8B,#n
a → Vd.8B
b → Vn.8B
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.16B,Vn.16B,#n
a → Vd.16B
b → Vn.16B
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.4H,Vn.4H,#n
a → Vd.4H
b → Vn.4H
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.8H,Vn.8H,#n
a → Vd.8H
b → Vn.8H
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.2S,Vn.2S,#n
a → Vd.2S
b → Vn.2S
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.4S,Vn.4S,#n
a → Vd.4S
b → Vn.4S
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Vd.2D,Vn.2D,#n
a → Vd.2D
b → Vn.2D
1 << n << 64
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.
SRSRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.
URSRA Dd,Dn,#n
a → Dd
b → Dn
1 << n << 64
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.8B,Vn.8B,#n
a → Vn.8B
0 << n << 7
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.16B,Vn.16B,#n
a → Vn.16B
0 << n << 7
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.4H,Vn.4H,#n
a → Vn.4H
0 << n << 15
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.8H,Vn.8H,#n
a → Vn.8H
0 << n << 15
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.2S,Vn.2S,#n
a → Vn.2S
0 << n << 31
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.4S,Vn.4S,#n
a → Vn.4S
0 << n << 31
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Vd.2D,Vn.2D,#n
a → Vn.2D
0 << n << 63
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.8B,Vn.8B,#n
a → Vn.8B
0 << n << 7
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.16B,Vn.16B,#n
a → Vn.16B
0 << n << 7
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.4H,Vn.4H,#n
a → Vn.4H
0 << n << 15
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.8H,Vn.8H,#n
a → Vn.8H
0 << n << 15
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.2S,Vn.2S,#n
a → Vn.2S
0 << n << 31
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.4S,Vn.4S,#n
a → Vn.4S
0 << n << 31
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Vd.2D,Vn.2D,#n
a → Vn.2D
0 << n << 63
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
v7/A32/A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Bd,Bn,#n
a → Bn
0 << n << 7
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Hd,Hn,#n
a → Hn
0 << n << 15
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Sd,Sn,#n
a → Sn
0 << n << 31
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
SQSHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Bd,Bn,#n
a → Bn
0 << n << 7
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Hd,Hn,#n
a → Hn
0 << n << 15
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Sd,Sn,#n
a → Sn
0 << n << 31
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
UQSHL Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.8B,Vn.8B,#n
a → Vn.8B
0 << n << 7
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.16B,Vn.16B,#n
a → Vn.16B
0 << n << 7
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.4H,Vn.4H,#n
a → Vn.4H
0 << n << 15
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.8H,Vn.8H,#n
a → Vn.8H
0 << n << 15
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.2S,Vn.2S,#n
a → Vn.2S
0 << n << 31
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.4S,Vn.4S,#n
a → Vn.4S
0 << n << 31
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Vd.2D,Vn.2D,#n
a → Vn.2D
0 << n << 63
Vd.2D → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
v7/A32/A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Bd,Bn,#n
a → Bn
0 << n << 7
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Hd,Hn,#n
a → Hn
0 << n << 15
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Sd,Sn,#n
a → Sn
0 << n << 31
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
SQSHLU Dd,Dn,#n
a → Dn
0 << n << 63
Dd → result
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d] = result;
A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN Vd.8B,Vn.8H,#n
a → Vn.8H
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
v7/A32/A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN Vd.4H,Vn.4S,#n
a → Vn.4S
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
v7/A32/A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN Vd.2S,Vn.2D,#n
a → Vn.2D
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
v7/A32/A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN Vd.8B,Vn.8H,#n
a → Vn.8H
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
v7/A32/A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN Vd.4H,Vn.4S,#n
a → Vn.4S
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
v7/A32/A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN Vd.2S,Vn.2D,#n
a → Vn.2D
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
v7/A32/A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN2 Vd.16B,Vn.8H,#n
r → Vd.8B
a → Vn.8H
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN2 Vd.8H,Vn.4S,#n
r → Vd.4H
a → Vn.4S
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN2 Vd.4S,Vn.2D,#n
r → Vd.2S
a → Vn.2D
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN2 Vd.16B,Vn.8H,#n
r → Vd.8B
a → Vn.8H
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN2 Vd.8H,Vn.4S,#n
r → Vd.4H
a → Vn.4S
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
A64
Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.
SHRN2 Vd.4S,Vn.2D,#n
r → Vd.2S
a → Vn.2D
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; for e = 0 to elements-1 element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift; Elem[result, e, esize] = element<esize-1:0>; Vpart[d, part] = result;
A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN Vd.8B,Vn.8H,#n
a → Vn.8H
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN Vd.4H,Vn.4S,#n
a → Vn.4S
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN Vd.2S,Vn.2D,#n
a → Vn.2D
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN Bd,Hn,#n
a → Hn
1 << n << 8
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN Hd,Sn,#n
a → Sn
1 << n << 16
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN Sd,Dn,#n
a → Dn
1 << n << 32
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN2 Vd.16B,Vn.8H,#n
r → Vd.8B
a → Vn.8H
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN2 Vd.8H,Vn.4S,#n
r → Vd.4H
a → Vn.4S
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.
SQSHRUN2 Vd.4S,Vn.2D,#n
r → Vd.2S
a → Vn.2D
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN Vd.8B,Vn.8H,#n
a → Vn.8H
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN Vd.4H,Vn.4S,#n
a → Vn.4S
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN Vd.2S,Vn.2D,#n
a → Vn.2D
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN Bd,Hn,#n
a → Hn
1 << n << 8
Bd → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN Hd,Sn,#n
a → Sn
1 << n << 16
Hd → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN Sd,Dn,#n
a → Dn
1 << n << 32
Sd → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN2 Vd.16B,Vn.8H,#n
r → Vd.8B
a → Vn.8H
1 << n << 8
Vd.16B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN2 Vd.8H,Vn.4S,#n
r → Vd.4H
a → Vn.4S
1 << n << 16
Vd.8H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.
SQRSHRUN2 Vd.4S,Vn.2D,#n
r → Vd.2S
a → Vn.2D
1 << n << 32
Vd.4S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift; (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
A64
Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.
SQSHRN Vd.8B,Vn.8H,#n
a → Vn.8H
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.
SQSHRN Vd.4H,Vn.4S,#n
a → Vn.4S
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.
SQSHRN Vd.2S,Vn.2D,#n
a → Vn.2D
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.
UQSHRN Vd.8B,Vn.8H,#n
a → Vn.8H
1 << n << 8
Vd.8B → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.
UQSHRN Vd.4H,Vn.4S,#n
a → Vn.4S
1 << n << 16
Vd.4H → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift; (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part] = result;
v7/A32/A64
Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.
UQSHRN Vd.2S,Vn.2D,#n
a → Vn.2D
1 << n << 32
Vd.2S → result
CheckFPAdvSIMDEnabled64(); bits(datasize*2) operand = V[n]; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; boolean sat; for e = 0 to elements-1 element = (Int(Elem